Well, there are probably several different ways to manage display data. I would typically use a 64 byte "display buffer" for 512 LEDs which is manipulated by MAIN and my ISR driver would pull data from that buffer to drive the displays as a background task.If this is the case how do I effectly do anything with this?
;******************************************************************
;
COLUMN equ h'20' ; column number (0..7)
COLPOS equ h'21' ; column ring counter (00000001)
;
SBuff equ h'38' ; scan buffer 30..37, 8 bytes
DBuff equ h'40' ; disp buffer 40..77, 56 bytes
WBuff equ h'78' ; work buffer 78..7E, 7 bytes
radix dec
;******************************************************************
;
; K8LH High Performance 9-pin Display Subsystem ISR Driver
;
; This subsystem hardware/software design supports from one
; to seven 8x8 display modules.
;
; One LED column in each of the seven 8x8 modules is driven
; during each 1.0-msec interrupt cycle for an overall 12.5%
; duty cycle and 125-Hz refresh rate.
;
; A minimum PWM 'on-time' of 1% provides a 10-usec window
; at the start of each interrupt cycle where the PWM signal
; drives the MIC5821 Output Enable lines high (display off)
; which allows me to use the RB7-RB0 column driver lines
; temporarily as MIC5821 <DAT> and <CLK> lines to load the
; seven MIC5821 shift registers.
;
; Serial data is clocked into seven MIC5821 shift registers
; in parallel by stuffing PORTB with eight data bytes, each
; containing <DAT> bits in b7 through b1 and a <CLK> bit in
; b0 which is preset to '0'.
;
; The 1% minimum PWM 'on' time limits maximum brightness to
; 99% but the 1% loss of brightness is inperceivable at the
; high end.
;
; 24 cycles, 4.8-usecs (20-MHz clock)
;
ISR_load_shift_registers
movff SBuff+7,LATB ; bit 7 byte [ddddddd0]
bsf LATB,0 ; clock data [ddddddd1]
movff SBuff+6,LATB ; bit 6 byte
bsf LATB,0 ;
movff SBuff+5,LATB ; bit 5 byte
bsf LATB,0 ;
movff SBuff+4,LATB ; bit 4 byte
bsf LATB,0 ;
movff SBuff+3,LATB ; bit 3 byte
bsf LATB,0 ;
movff SBuff+2,LATB ; bit 2 byte
bsf LATB,0 ;
movff SBuff+1,LATB ; bit 1 byte
bsf LATB,0 ;
movff SBuff+0,LATB ; bit 0 byte
bsf LATB,0 ;
;
; resume PORTB column driver duties before PWM goes low and
; advance the column ring counter for the next cycle
;
; 3 cycles, 0.6-usecs
;
comf COLPOS,W ; invert bits (only 1 bit low)
movwf LATB ; setup PORTB column drivers
rlncf COLPOS,F ; advance column ring counter
;******************************************************************
;
; build the eight '5821 shift register bytes in SBuff for the
; next interrupt cycle. first copy the correct seven display
; buffer bytes for the next interrupt cycle and put them into
; the WBuff work buffer. then combine all of the b7 bits, b6
; bits, b5 bits, etc., into their own bytes in the eight byte
; SBuff shift register data buffer.
;
; step <1>
; copy 7 display column data bytes into the WBuff work buffer
;
; 25 cycles, 5.0-usecs
;
ISR_Display_Prep
lfsr 0,DBuff ; FSR0 = address DBuff[0,0]
incf COLUMN,F ; Column++
bcf COLUMN,3 ; Column %= 8
movf COLUMN,W ; WREG = Column (0..7)
movff PLUSW0,WBuff+0 ; WBuff[0] = DBuff[0,Column]
addlw 8 ;
movff PLUSW0,WBuff+1 ; WBuff[1] = DBuff[1,Column]
addlw 8 ;
movff PLUSW0,WBuff+2 ; WBuff[2] = DBuff[2,Column]
addlw 8 ;
movff PLUSW0,WBuff+3 ; WBuff[3] = DBuff[3,Column]
addlw 8 ;
movff PLUSW0,WBuff+4 ; WBuff[4] = DBuff[4,Column]
addlw 8 ;
movff PLUSW0,WBuff+5 ; WBuff[5] = DBuff[5,Column]
addlw 8 ;
movff PLUSW0,WBuff+6 ; WBuff[6] = DBuff[6,Column]
;
; step <2>
; build SBuff for next display interrupt cycle. all of the
; b0 bits in one byte, b1 bits in the next byte, and so on.
; bit 0 in each byte is preset to '0' to drive the CLK line
; low on the seven MIC5821 drivers as each byte is written
; to PORTB in the ISR_load_shift_registers routine.
;
; 145 cycles, 29.0-usecs
;
lfsr 0,SBuff ; shift register buffer address
V1 clrf INDF0 ; for (n=0; n<8; ++n)
rrcf WBuff+0,F ; WBuff[0] >>= 1
rrcf INDF0,F ; SBuff[n] >>= 1 + C*128
rrcf WBuff+1,F ; WBuff[1] >>= 1
rrcf INDF0,F ; SBuff[n] >>= 1 + C*128
rrcf WBuff+2,F ; WBuff[2] >>= 1
rrcf INDF0,F ; SBuff[n] >>= 1 + C*128
rrcf WBuff+3,F ; WBuff[3] >>= 1
rrcf INDF0,F ; SBuff[n] >>= 1 + C*128
rrcf WBuff+4,F ; WBuff[4] >>= 1
rrcf INDF0,F ; SBuff[n] >>= 1 + C*128
rrcf WBuff+5,F ; WBuff[5] >>= 1
rrcf INDF0,F ; SBuff[n] >>= 1 + C*128
rrcf WBuff+6,F ; WBuff[6] >>= 1
rrcf POSTINC0,F ; SBuff[n] >>= 1 + C*128
btfsc FSR0L,3 ;
bra V1 ;
;******************************************************************
;
DBuff equ h'00' ; disp buffer 00..3F, 64 bytes
WBuff equ h'80' ; work buffer 80..85, 6 bytes
RowPos equ h'86' ; ISR, 16 bit row ring counter
Row equ h'88' ; ISR, row number (0..15)
Counter equ h'89' ; ISR, counter
;******************************************************************
radix dec
;******************************************************************
;
; K8LH Experimental 16x32 6-pin Display Subsystem ISR Driver
;
; This subsystem driver was designed for an OEM 16x32 display
; that uses three 16 bit serial-to-parallel driver IC's.
;
; One 32 LED row is driven each 1.0-msec interrupt cycle for
; an overall 6.25% duty cycle and 62.5-Hz refresh rate.
;
; Serial data is clocked into three 16 bit shift registers
; in parallel by stuffing PORTB with 16 data bytes, each
; containing <DAT> bits in b0, b1, and b2, a <CLK> bit in b3
; which is preset to '0', and a <LAT> bit in b4 which is
; preset to '1'. This driver loads the shift registers with
; bit 15 data first.
;
; RB0 = DAT line on row driver IC
; RB1 = DAT line on 1st column driver IC
; RB2 = DAT line on 2nd column driver IC
; RB3 = CLK line on all 3 ICs
; RB4 = LAT line on all 3 ICs
; RB5 = STB line on all 3 ICs
;
; 263 cycles, 52.6 usecs, 5.26% "overhead" (20 MHz clock)
; 33.2 usecs, 3.32% "overhead" (32 MHz clock)
;
ISR_load_shift_registers
clrf FSR1H ;
rlncf Row,W ; row number (0..15) x4
rlncf WREG,W ;
movwf FSR1L ; FSR1 = DBuff(Row).byte(0)
movff POSTINC1,WBuff+0 ; b07..b00 display data
movff POSTINC1,WBuff+1 ; b15..b08 display data
movff POSTINC1,WBuff+2 ; b23..b16 display data
movff POSTINC1,WBuff+3 ; b31..b24 display data
movff RowPos+0,WBuff+4 ; b07..b00 ring counter
movff RowPos+1,WBuff+5 ; b15..b08 ring counter
bsf Counter,4 ; Cntr = 16
v0 movlw b'00000010' ; preload WREG
rlcf WBuff+0,F ; rlcf lo byte, DBuff(Row,0)
rlcf WBuff+1,F ; rlcf hi byte, DBuff(Row,1)
rlcf WREG,F ; pick up b2 (2nd column SR)
rlcf WBuff+2,F ; rlcf lo byte, DBuff(Row,2)
rlcf WBuff+3,F ; rlcf hi byte, DBuff(Row,3)
rlcf WREG,F ; pick up b1 (1st column SR)
rlcf WBuff+4,F ; rlcf lo byte, RowPos
rlcf WBuff+5,F ; rlcf hi byte, RowPos
rlcf WREG,F ; pick up b0 (row SR)
movwf LATB ; update port, [--010ddd]
bsf LATB,3 ; toggle <CLK> [--011ddd]
decfsz Counter,F ; all 16 iterations?
bra v0 ; no, branch, else
bcf LATB,4 ; toggle <LAT> [--001ddd]
bsf LATB,4 ; tobble <LAT> [--011ddd]
;
; advance Row variable and RowPos ring counter for next cycle
;
incf Row,F ; Row++
bcf Row,4 ; Row % 16 (well, sort of)
rrcf RowPos+0,W ; rrcf lo byte into W to save C
rrcf RowPos+1,F ; rrcf hi byte
rrcf RowPos+0,F ; rrcf lo byte
retfie FAST ;
;******************************************************************
;
Init_display
lfsr 0,DBuff ; clear display buffer & vars
iloop clrf POSTINC0 ;
movf FSR0L,W ;
xorlw 0xC0 ; 00..BF cleared?
bnz iloop ; no, branch, else
clrf RowPos ; setup RowPos ring counter
clrf RowPos+1 ;
bsf RowPos+1,7 ; RowPos = %1000000000000000
movlw b'00010000' ;
movwf PORTB ; set LAT (B4) pin hi
clrf TRISB ; PORTB all outputs
return ;
DIM Display(16) as LongWord
Display(15) = %00000000000000000000000000000000
Display(14) = %01111111111111110000000000000000
Display(13) = %01111111111111110000000000000000
Display(12) = %01111000000011110000000000000000
Display(11) = %01111000000011110000000000000000
Display(10) = %01111000000000000000000000000000
Display(9) = %01111000111100000000000000000000
Display(8) = %01111111111100000000000000000000
Display(7) = %01111111111100000000000000000000
Display(6) = %01111000111100000000000000000000
Display(5) = %01111000000000000000000000000000
Display(4) = %01111000000011110000000000000000
Display(3) = %01111000000011110000000000000000
Display(2) = %01111111111111110000000000000000
Display(1) = %01111111111111110000000000000000
Display(0) = %00000000000000000000000000000000
PAUSE Delay
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