I've been playing around with a pic again and needed to access the PPS SFRs located sequentially in memory at 0xF18. The first one is RB0PPS and to access them as an array you can do,
((unsigned char *)&RB0PPS)[7]=0x01;
This would write 1 to RB7PPS. This would enable the CLC1 output on RB7.
On the pic24 they have a locking mechanism for the PPS in the OSCCON reg... BUT!! they have a write enable sequence for the OSCCON register... AARRGGHH..