8051 Memory Mapped

[electroRF]

Hi,

I got this 8051 uC, which has the following 3 Physical Memories:

1. 64KB Program Flash Memory
2. 8KB SRAM
3. Memory Mapped Registers

It is said in the datasheet (page 30) that there are 4 memories which are mapped onto the above physical memories.
the 4 memories are:
1. 64KB Program Flash Memory
2. 256B Data Memory Space
3. XDATA Data Memory Space
4. SFRs

Could you please explain what does it mean that these 4 memories are mapped onto the 3 physical memories?

Also - what are memory mapped registers?

You may also refer to some link which explains it - I read Wiki's term but understand very little.

Thanks a lot.

 

[Ian Rogers]

Are you serious!!! What on earth have we been going on about in your other thread!!!!

I'm sure I answered these questions already.. Here read this....

 

[electroRF]

Hi Ian,

I'm firstly very sorry for letting you think that I'm asking already-answered questions.

The truth is, i find myself reading the datasheet of the uC, and very frequently i run into terms which i'm not familar with.

and actually what i'm doing is spending X time on reading the datasheet, and 100X time googling things up.

It is very frustrating.

Let me tell you something.

I've already encountered that PDF you shared and i think i actually have every memory-mapped related link read in my laptop.

But, I just don't manage to understand what it is - there's no 'for-beginners' explanation about it.

I'd be HAPPY to get some good tutorial, as i'm very frustrating reading the datasheet and understand nothing.

 

[Ian Rogers]

Code space...... Here is a linear memory space it ranges from 0x0 to 0xFFFF....
Data space..... There are TWO different physical data spaces.

Internal data space...
External data space..
​

Internal Data space

Starts at 0x0... R0 -R7 bank(1)
Then from. 0x8.. R0 -R7 bank(2)
Then from. 0x10.. R0 -R7 bank(3)
Then from. 0x18.. R0 -R7 bank(4)
Then from. 0x20.. Bit accessible GPR's
Data memory starts at 0x30.. through 0x7F

Special purpose registers at from 0x80 up!!! ( this memory is also bit accessible.. )
​

External Data space

Starts at 0x0 and ends 64k (0xFFFF)​

 

[electroRF]

Hi Ian,
First of all, thank you very very much!

I think that is clears a lot of the things i did not understand.

Thanks to you!

Am I correct that there are the following 3 Physical Memories of the 8051 uC:

1. 8KB Physical SRAM
-- a. 256B of it are fast access - 1 instruction cycle for read/write
-- b. (8KB-256B) of it is slow access

2. 128B Registers (SFR / RF) - Is there a seperate memory for these 128B inside the chip?

3. 128KB Flash Program Memory


This is the memory map:

It is said there that the part of the SRAM from 0xE000 to 0xFF00 consists of Program Memory - does it mean that this part of the SRAM is the cache, which pre-fetchs insructions from the Code Memory?
(Cache is supposed to be fast, but it is said there SLOW Access RAM)

How come the same RAM has 'FAST Access' Part and 'SLOW Access' Part?

 

[Ian Rogers]

Slow access is external memory.... Just because there is oodles of memory inside the micro doesn't mean it's treated as internal memory!!

If there is more than 256 bytes of SRAM it is treated as external ram... There is usually about 128 bytes for the user... This is called "Direct Access Ram" and use the MOV command, Single instruction fetch... If you access any RAM above this figure you need to use the MOVX command... This is "Indirect Access Ram" double instruction fetch...

Ti and many others are just pitching all the external peripherals into a single chip.

 

[electroRF]

Thank you very much Ian!!

It's great reading your answers!

So I see that there's the top 256Bytes which are "Direct Access RAM" which are INTERNAL and are single instruction, and there are the rest of the RAM which is EXTERNAL, and is double instruction, right?

Could you please refer to what does it mean that the External RAM has Program Memory?

Thank you

 

[Ian Rogers]

You would need to go into how Ti have mapped the memory... It's a science I never went into... There are ways of mapping a single flash chunk into different sections... The micro core see's what Ti want's it to see... There are documents on the web, but as I said, I never went that deep...

 

[NorthGuy]

I think you need to grasp the basic concept. Processor doesn't know where the physical memory is. All it does, is sets the address on an address bus and sets up a signal that it wants the memory read. It's up to the perihery memory devices (regardless of whether on the same chip or not) to read the address on the bus, fetch the data and put in on data bus. Once this is done, the device signals to the processor and the processor does with the data whatever the instruction says to do. Processor may have to wait for the memory to respond, so it may add some time to the execution.

Memory can be put on the same chip or outside of the chip. It may be ROM or RAM. It may be slow or fast. But processor knows nothing about that. You look at your map and figure that out.

What happens if I instruct the processor to fetch XDATA from address 0xdf82. What device will respond to the call? You look on the left side of your map and you see the XDATA block. You follow it to the right and see that this address is mapped to SFR. The processor's call will be answred by a device connected to the SFR 0xo2 (note that this could've been accessed in a different way, through SFR data space 0x82).

And conversely, how do I access RAM at address 0x1f10? Find this address on the right and follow to the keft. There are two ways to access this memory! XDATA instruction with address 0xff10 or fast DATA instruction at address 0x10. Take your pick.

Or you want to access RAM at address 0x0500? Unfortunately there's only one way - through XDATA at address 0xe500. That's why this part of the memory is called slow.

Or you want to access flash memory at address 0xf000. How do you do that? No way. Processor doesn't have any access to it through its memory spaces. Must be some other way to access it. Look at the datasheet.

Pick a different device. Look. Everything is different, but the principle is the same.

 

[electroRF]

Ian, NorthGuy thank you very much!


NorthGuy,
I'm speechless, i really thank you for this great post which helped me understand a lot!

 

[electroRF]

NorthGuy

Could you please mention why the memory mapping (which you awesome-ly explained) is required?

i.e. if you could address an SFR by its address - 0x82 - why do you need it to be mapped to XDATA (where you access it by other address 0xDF82)?

 

[NorthGuy]

i.e. if you could address an SFR by its address - 0x82 - why do you need it to be mapped to XDATA (where you access it by other address 0xDF82)?

I don't think there's any particular reason to do this from the programming viewpoint. They probably did this because it was a convenient way to do technologically.

 

[misterT]

Using 8-bit address is more efficient on 8-bit processor, but you need 16 bits to address the whole memory. So some important memory locations (registers) can be addressed with 8-bit address.

 

[electroRF]

Thank you very much guys

I really appreciate your help!

I thought there was a "superior" reason for mapping.

Is it correct to say that the SRAM which the 8051 uses have 2 'different hardware' sections so that: (is it due to hardware inside the SRAM?)
0xFF00 - 0xFFFF : fast access
0xE000 - 0xFF00 : slow access

Is it common in RAMs that serve embedded uC that they have fast access section and slow access section?

 

[Ian Rogers]

Is it common in RAMs that serve embedded uC that they have fast access section and slow access section?

No! I think Intel are the only chip manufacturers with this memory thing ( apart from the clones Z80 and such)!!! The 8051 was deigned oodles of years ago when there wasn't many applications for micro's.

To access external memory or external anything for that matter , in the original 8051, requires manipulation of signals to get the data into the processor... You needed to use a latch to separate the Address bus from the Data bus as they are both on the same port!!! I don't know how they do it when extra data is internal!!! This is why they have this elaborate mapping system... The addressing of memory will differ from chip to chip... Atmel will have a different method than Phillips!!!

The Motorolla and AVR's have linear memory. so There isn't this problem.... Pic uses banks of registers!! I think we're up to about 12 banks now.... But even these have different properties... For instance some memory locations can be "Bit accessed" whilst others cannot!!

Its the job of the programmer to understand addressing modes before writing for a particular chip!!