I'm unsure of exactly what you wish to do, but I think you want to 'automatically' load in your 4 bits from the internal shift registers to the latch output... correct? I can only assume you want to use 2 lines, serial data, and serial clock - with the 'latch' being derived from the serial clock.
Now, its easy to get confused as different schematics/datasheets have different names for 'serial clock' and 'load clock'. The '594 and '595 generally use SRCLK and RCLK. You must be consistant with names, here I am going to use 'shift clock' and 'load' to indicate to clock to shift bits into the shift register, and 'load' for the latch out the output.
In order to 'latch' (using 'load', or RCLK as it is in the datasheet) after 4 bits have been shifted in, you should make this line high after the 4th serial clock, but before the 5th. I suspect your 4 bit counter is outputting a high as soon as the count reaches 4, effectively, loading the latch instantly *as* your 4th bit is loaded. A monostable is a good way of delaying, but relies on analogue timing components.
You may be able to do this with a single transistor with your counter. Use a PNP with its emitter (positive) connected to the output of your 4-bit counter. And its base connected to your shift clock via a resistor. It's collector is connected to your 'load' line. It'll make a crude logic gate, meaning its output will only be 'high', when your count is '4', and your clock is '0'. It'll delay the 'load' line by 1/2 of your shift clock. Although, with this method you may have to reset the counter afterwards... since the counter will start at '0', after 4 clocks, it'll be '4', after another 4...it'll be 8. The above method only works if you're counter has a single 'pulse' output :/
What binary counter did you use?