4-bit up/down counter using jk flip flops

[gordo]

hey guys! i need help designing a 4 bit counter using jk flip flops. It has to count 0, 1, 3, 4, 6, 7, 9, 10, 12, 13, 14, 15. The counter has unused states 2, 5, 8, 11 and a function bit to count either up or down. I am using 74LS76A Dual jk flip flops and any other combinational circuit to implement this sequential circuits. Any ideas you can give me will be appreciated. Thanks!!!

 

[Russlk]

Do you mean that the counter has only 12 states and the 2nd clock pulse produces 0011 at the output?

 

[gordo]

the counter will have does 12 states and it must have an extra input that will make it count forward and backwards

 

[ljcox]

I'll post some help for you tomorrow. Can't spare the time now.

Len

 

[gordo]

This is what i got so far. The JK flip flop can be turn into a T flip flop jumping JK together. Then I made 2 truth tables stating one for the up count and one for the down count. then I made 4 Karnaugh maps for up count and 4 for down count. The use a 2 to 1 multiplexer to switch between the up and down count. Im gonna implement it tomorrow. Any other ideas I will appreciate it. Also I have the 74LS47 BCD to seven segment decoder but I want a binary to seven segment decoder to show from 0 to 15 in the seven segment display, does anyone knows if that decoder exists???

 

[ljcox]

Here is the first installment. I'll post the next one tomorrow.

I'll leave you to fill in the blanks.

The next step is to draw the Karnaugh maps for all of the J and K inputs.

The Up/Down can be included in the Karnaugh maps in order to minimise the gating.

Len

 

[ljcox]

Here are the Karnaugh Maps and Boolean expressions for the fourth Flip Flop

 

[ljcox]

Attached is the gating for the fourth Flip Flop.

 

[gordo]

thanks for the help, my design its almost working. when i have time I will post it.