4-bit parity generator

The question says,
Design a circuit that takes a serial data stream from data in input. The output of the
circuit is high if data in on previous four clocks has even number of ones. E.g. the
output on nth clock is high if the data in on clocks (n-1), (n-2), (n-3) and (n-4) has
even number of ones.

Can anyone please help me with the State Machine of the same ?

Thanks.

RESET/IDLE: parity=TRUE; start_bit detected? { goto RECEIVE_BIT; }

RECEIVE_BIT: bit_count ++; is bit = '1'? { parity = not parity;} is bit_count =4? { output parity; goto RESET/IDLE;}