I'm happy to hear of your progress. Realize that when you use test resistors, it's not the same as using a LD. When you use a test resistor the voltage developed across the test resistor is the current through the test resistor times the value of the test resistor. However, the voltage across the LD will never exceed approx 2V. The highest voltage the circuit can deliver across the load is, at best 8.6 - 2.5= 6.1 volts. The actual voltage the circuit can deliver to the load will be less than 6.1V due to minimum resistance of the FET, the threshold voltage of the FET, other FET characteristics, and the minimum voltage the op amp can provide. So, if you set the current to 250 mA and your test resistor is 25 ohms, the voltage drop required across the test resistor is .25 * 25 = 6.25V, which is a voltage greater than the circuit can deliver to the load, and so, the current will fall below the value you set it at -- as you indeed discovered. Try using three ordinary silicon diodes in series instead of test resistors to simulate the LD, and then adjust your current to test the current through the load. Use the IRF9520 and mount it to a heat sink to keep it cool. You should not need a large heat sink, as the power it has to dissipate is about 1 watt.
I wouldn't use C4 where you added it. It will result in a large spike of current through the LD because the reference voltage at the + input of U1 will take a long time time to reach steady state level. I realize that you have a comparator there, presumably to prevent turn on for a while, but why put a current spike in there only to use a comparator to quench it? I'd use the configuration in the original schematic. The use of Q2 to disable the Op amp in your schematic doesn't look right at all, also.
The issue that the designer of the original schematic was most trying to address was the turn-on, transient spikes on the LD, not overcurrent protection.