Rohit Chatterjee
New Member
Okk i hav this assignment which i just cant figure out.....i hav basic ideas about op-amp circuits but hav nvr solved a design problem employing frequency compensation....please give sum hints.....here goes the problem....
"Design a 2-stage single-ended op-amp using 0.18 mu-m CMOS technology thats has a dc gain
of at least 500,and a unity gain frequency of 100 MHz with a load of 5 pF and 5 k-ohm
in parallel.Design the 2nd stage common source amplifier to have a sufficiently high dc
gain while driving the desired load capacitance and a sufficiently high 2nd pole while
driving the desired load capacitance.Use a scaled version of your single stage op-amp
design from above for the input stage.Use a suitable compensation capacitor.All parasitic
poles and zeroes should be at least twice the unity gain frequency.Ensure that there is
no systematic offset because of the 2nd stage bias.Add a zero cancelling resistor.
0.18 mu-m technology parameters: V_Tn=0.5V,V_Tp=0.5V,Kn=300 mu-A/(V^2),Kp=75 mu-A/(V^2),
Vdd= 1.8V,Lmin=0.18 mu-m,Wmin=0.24 mu-m.
Ignore body effect and 1/f noise."
"Design a 2-stage single-ended op-amp using 0.18 mu-m CMOS technology thats has a dc gain
of at least 500,and a unity gain frequency of 100 MHz with a load of 5 pF and 5 k-ohm
in parallel.Design the 2nd stage common source amplifier to have a sufficiently high dc
gain while driving the desired load capacitance and a sufficiently high 2nd pole while
driving the desired load capacitance.Use a scaled version of your single stage op-amp
design from above for the input stage.Use a suitable compensation capacitor.All parasitic
poles and zeroes should be at least twice the unity gain frequency.Ensure that there is
no systematic offset because of the 2nd stage bias.Add a zero cancelling resistor.
0.18 mu-m technology parameters: V_Tn=0.5V,V_Tp=0.5V,Kn=300 mu-A/(V^2),Kp=75 mu-A/(V^2),
Vdd= 1.8V,Lmin=0.18 mu-m,Wmin=0.24 mu-m.
Ignore body effect and 1/f noise."
