18F SPI works in debug not in real mode

#define _XTAL_FREQ 20000000

#include <xc.h>



// CONFIG1H
#pragma config OSC = HS  // Oscillator Selection bits (Internal oscillator block, port function on RA6 and RA7)
#pragma config FCMEN = OFF  // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
#pragma config IESO = OFF  // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)

// CONFIG2L
#pragma config PWRT = OFF  // Power-up Timer Enable bit (PWRT disabled)
#pragma config BOREN = BOHW  // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled))
#pragma config BORV = 3  // Brown-out Reset Voltage bits (VBOR set to 2.1V)

// CONFIG2H
#pragma config WDT = OFF  // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
#pragma config WDTPS = 32768  // Watchdog Timer Postscale Select bits (1:32768)

// CONFIG3H
#pragma config PBADEN = OFF  // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
#pragma config LPT1OSC = ON  // Low-Power Timer 1 Oscillator Enable bit (Timer1 configured for low-power operation)
#pragma config MCLRE = OFF  // MCLR Pin Enable bit (RE3 input pin enabled; MCLR disabled)

// CONFIG4L
#pragma config STVREN = ON  // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
#pragma config LVP = OFF  // Single-Supply ICSP Enable bit (Single-Supply ICSP enabled)
#pragma config BBSIZ = 1024  // Boot Block Size Select bits (1K words (2K bytes) Boot Block)
#pragma config XINST = OFF  // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))

// CONFIG5L
#pragma config CP0 = OFF  // Code Protection bit (Block 0 (000800-003FFFh) not code-protected)
#pragma config CP1 = OFF  // Code Protection bit (Block 1 (004000-007FFFh) not code-protected)
#pragma config CP2 = OFF  // Code Protection bit (Block 2 (008000-00BFFFh) not code-protected)
#pragma config CP3 = OFF  // Code Protection bit (Block 3 (00C000-00FFFFh) not code-protected)
#pragma config CP4 = OFF  // Code Protection bit (Block 4 (010000-013FFFh) not code-protected)
#pragma config CP5 = OFF  // Code Protection bit (Block 5 (014000-017FFFh) not code-protected)

// CONFIG5H
#pragma config CPB = OFF  // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
#pragma config CPD = OFF  // Data EEPROM Code Protection bit (Data EEPROM not code-protected)

// CONFIG6L
#pragma config WRT0 = OFF  // Write Protection bit (Block 0 (000800-003FFFh) not write-protected)
#pragma config WRT1 = OFF  // Write Protection bit (Block 1 (004000-007FFFh) not write-protected)
#pragma config WRT2 = OFF  // Write Protection bit (Block 2 (008000-00BFFFh) not write-protected)
#pragma config WRT3 = OFF  // Write Protection bit (Block 3 (00C000-00FFFFh) not write-protected)
#pragma config WRT4 = OFF  // Write Protection bit (Block 4 (010000-013FFFh) not write-protected)
#pragma config WRT5 = OFF  // Write Protection bit (Block 5 (014000-017FFFh) not write-protected)

// CONFIG6H
#pragma config WRTC = OFF  // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
#pragma config WRTB = OFF  // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
#pragma config WRTD = OFF  // Data EEPROM Write Protection bit (Data EEPROM not write-protected)

// CONFIG7L
#pragma config EBTR0 = OFF  // Table Read Protection bit (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR1 = OFF  // Table Read Protection bit (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR2 = OFF  // Table Read Protection bit (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR3 = OFF  // Table Read Protection bit (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
#pragma config EBTR4 = OFF  // Table Read Protection bit (Block 4 (010000-013FFFh) not protected from table reads executed in other blocks)
#pragma config EBTR5 = OFF  // Table Read Protection bit (Block 5 (014000-017FFFh) not protected from table reads executed in other blocks)

// CONFIG7H
#pragma config EBTRB = OFF  // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)

#define CS LATCbits.LATC6
#define WCOLIND LATCbits.LATC7


void spi(unsigned char myData);
void delay1s(void);


void main(void) {
  TRISB = 0x00;
  CS = 1;
  TRISCbits.TRISC5 = 0;
  TRISCbits.TRISC4 = 1;
  TRISCbits.TRISC3 = 0;
  TRISCbits.TRISC6 = 0;
  TRISCbits.TRISC7 = 0;
  
  TRISAbits.TRISA5 = 0;
  
  TRISCbits.TRISC0 = 1;
  
  SSPSTATbits.SMP = 0;
  SSPSTATbits.CKE = 1;
  
  SSPCON1bits.SSPEN = 0;
  SSPCON1bits.CKP = 0;
  SSPCON1bits.SSPM0 = 0;
  SSPCON1bits.SSPM1 = 0;
  SSPCON1bits.SSPM2 = 0;
  SSPCON1bits.SSPM3 = 0;
  
  SSPCON1bits.SSPEN = 1;
  
  while(1)
  {
  spi(0xA0);
  spi(0xA1);
  spi(0xA2);
  spi(0xA3);
  spi(0xA4);
  spi(0xA5);
  spi(0xA6);
  spi(0xA7);
  
  
  
  }
  
  
  return;
}

void spi(unsigned char myData)
 {  
SSPCON1bits.WCOL = 0;
CS = 0;  
SSPBUF = myData;  // write byte to SSPBUF register
while(!SSPSTATbits.BF);
delay1s();
PORTB = SSPBUF;
CS = 1;
delay1s();
}

void delay1s(void){
  for(int x = 0; x<1002; x++){
  __delay_ms(1);
  }
}