list p=16f1827
#include <p16f1827.inc>
__CONFIG _CONFIG1, _FOSC_XT & _WDTE_OFF & _PWRTE_ON & _MCLRE_OFF & _CP_OFF & _CPD_OFF & _BOREN_ON & _CLKOUTEN_OFF & _IESO_OFF & _FCMEN_OFF
__CONFIG _CONFIG2, _WRT_OFF & _PLLEN_OFF & _STVREN_OFF & _BORV_19 & _LVP_OFF
;------------------------------------------------------------------------------
; VARIABLE DEFINITIONS
;
; Available Data Memory divided into Bank 0-15. Each Bank may contain
; Special Function Registers, General Purpose Registers, and Access RAM
;
;------------------------------------------------------------------------------
CBLOCK 0x20 ; Define GPR variable register locations
dc1 ; User variables allocated contiguously
dc2 ;
dc3 ;
ENDC
ORG 0x0000 ; processor reset vector
GOTO START
start
banksel cm1con0
bcf cm1con0,7 ;turn off comparators
bcf cm2con0,7 ;
banksel adcon0
bcf adcon0,0 ;A2D off
banksel ansela
clrf ansela ;porta digital i/o
clrf anselb ;portb digetal i/o
banksel trisa
clrf trisa ;porta output
clrf trisb ;portb output
banksel porta
clrf porta ;outputs LO
clrf portb
Main
BSF PORTB,2 ; Turn on LED connected to RB2
movlw .50 ; 500 ms delay
CALL adj_delay_ms
BCF PORTB,2 ; Turn off LED connected to RB2
movlw .50
CALL adj_delay_ms
GOTO Main
;------Adjustable delay-----10-2550 ms(2.55 seconds)------------
; delay = W x 10ms
; enter with multiplier in WREG before CALL
adj_delay_ms
banksel dc3 ; Wx10.015ms
movwf dc3
dly2 movlw .13 ; repeat inner loop 13 times
movwf dc2 ; -> 13x(767+3)-1 = 10009 cycles
clrf dc1 ; inner loop = 256x3-1 = 767 cycles
dly1 decfsz dc1,f
goto dly1
decfsz dc2,f ; end middle loop
goto dly1
decfsz dc3,f ; end outer loop
goto dly2
return
END