120kHz oscillation in received DALI signal

[Flyback]

Hi,
We have a DALI communication setup. To be brief, DALI is basically square wave transmissions at 1200Hz.
A DALI bus is pulled down and released at the 1200Hz frequency, as in the attached schematic. (LTspice sim also attached)

In our DALI circuit, the node RA3 is following the transmission of the DALI bus, and is obviously an inverted form of it…however, within the high-going pulses at RA3, there is an approximately 120kHz oscillation….which is rendering the comms not working.

I believe that this 120kHz oscillation is caused by the fact that due to the bridge rectifier, the DALI bus is not fully getting actively pulled down (after the bridge) for the “Low” pulses, and therefore the NPN at RA3 is turning on and off repeatedly at 120kHz as its base current starts to fall to around its off level.

Would you agree, that the best way to stop this oscillation would be to reduce the Base_emitter resistor down to 1k? (This would also mean reducing the resistor R18 down to 2k2 so that the voltage isn’t divided down so much. R18 and R19 are 0603 size)

The attached simulation doesn’t show this unwanted 120kHz oscillation happening.
(by the way, there is also a 60W offline led driver SMPS on the same PCB as the DALI receiver part of the circuit shown)

 

[rjenkinsgb]

I'd add a low value cap between base and emitter on the receiving transistor, to filter both remote and local noise.
The data rate is only 1200 baud so a time constant of eg. 10 - 20 uS should have no effect at all on the wanted signal while significantly reducing possible interference.

You also need a load resistor directly across the bridge, eg. another 10K.
As shown, it will only discharge the capacitance of the bridge output to the point the zener stops conducting, so possibly 6.8V, and then the slightest noise causing a voltage increase may cause the transistor to turn on again.

Ensuring a full discharge gives the best possible noise margin.

 

[Flyback]

By the way, the attached shows the 120khz noise that we are seeing on RA3....top is what we should see, bottom is what we get..

The following on page 3 shows the DALI circuit idea we are looking at

https://ww1.microchip.com/downloads/en/AppNotes/01465A.pdf

 

[Flyback]

You also need a load resistor directly across the bridge, eg. another 10K.

Thanks, what about the following adjustment?…now we have reduced the gain of the first NPN stage, making it a follower. We have also made the base_emitter resistor 10 times less.

Also added the DALI bus load , and the cap at the NPN base_emitter.
(pdf schem and LTspice sim attached)

(Incidentally , On the previous board, the original circuit of the top post worked absolutely fine, but we did not have the bridge rectifier then.)

 

[rjenkinsgb]

There was no need to make other changes as well??

Your circuit is no longer DALI compliant as the current from the bus will be far more than the permitted 2mA.

 

[Flyback]

Your circuit is no longer DALI compliant as the current from the bus will be far more than the permitted 2mA.

Thanks, sorry i forgot to say we dont have to comply with the 2mA thing as theres only one device on the dali bus.

 

[alec_t]

there is also a 60W offline led driver SMPS on the same PCB as the DALI receiver part of the circuit shown

Does the switching frequency of that driver match the spurious oscillation frequency?

 

[Flyback]

Thanks, no the f(sw) is 75-100khz.

The attached (pdf schem and LTspice sim) are all the possible ways of fixing this DALI comms (Tx and RX) circuit.....we hope we only have to resort to circuit "A"

 

[rjenkinsgb]

What happens if you use a logic FET such as a 2N7000 in the very first circuit, in place of the bipolar transistor?

 

[Flyback]

Thanks,
by the way, the following circuit also works fine, but we dont want a bulky opto in there as we dont need the isolation.
(ltspice and pdf attached)

 

[rjenkinsgb]

An opto is pointless when the input and output are connected to the same ground.

The DALI spec. says something like a "1" as 16V +/- 6V or something like that.
The receiver should be designed so the input transistor can not get any base current for a voltage lower the minimum, around 10V.

Working around the original circuit:
Subtracting the zener and transistor base voltages, that's around 3.2V across the upper resistor at the 10V threshold; ver close to 1/3 of 10V.
Try a direct two resistor voltage divider, 4K7 upper and 10K lower (or 3K3 and 6K8, or lower in a similar ratio).
Then connect the 6.2V zener from the resistor junction to base and eg. 47K base to emitter.

You could also add a 1n cap from the resistor junction to ground.