• Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.
Resource icon

PIC 16F and Register Banking Explained 2012-03-25

PIC 16F And iRAM Banking

By Jon Wilder

As some of you have noticed, the internal RAM in the PIC 16F appears to be arranged in “banks”. Each bank holds 128 RAM registers total. The first 128 RAM locations are in bank 0, the next 128 RAM locations are in bank 1, so on and so forth.

But hold on...is this REALLY the case? If it is, then why is it that when we indirect address via the FSR pointer register that we can access 256 RAM locations without having to bank select?

Because this isn't what's really going on.

iRAM on a PIC 16F is a contiguous space. It starts at address 0x000 and ends at 0x1FF. However, some locations within this space are unimplemented. The datasheet states that iRAM is divided up into 4 banks of 128 registers each. Why is this?

The reason is because there is a limitation in the instructions that the PIC uses to address iRAM locations (basically all of the instructions which have an “f” in them). Byte-oriented instructions which address the registers are in the format of -

|         OPCODE        | DEST | A6 | A5 | A4 | A3 | A2 | A1 | A0|
| x | x | x | x | x | x | 0/1  | f  | f  | f  | f  | f  | f  | f |
Bit-oriented operations (bsf, bcf, btfss and btfsc) are in the format of -

|     OPCODE    |Bit Number |A6 |A5 |A4 |A3 |A2 |A1 |A0 |
| x | x | x | x | b | b | b | f | f | f | f | f | f | f |
The opcode is the instruction itself. In the first table, DST is the destination bit that tells the PIC whether to store the result in W (0) or in the file register (1) who's address is in bits AD0-AD6. In the second table, the 4 MSBs are the instruction, the 3 “BIT” bits are the bit that the instruction will be executed on (0-7), while AD0-AD6 are the address in the file where the bit to be manipulated resides.

Notice AD0-AD6...that's only 7 address bits!

Basically, instructions which directly address the iRAM register locations can only provide 7 of the address bits. Since 7 bits can only count to 0x7F (decimal 127), this limits the instruction itself to only access 128 RAM locations on its own...hence the limitation.

So how can we overcome the limitation so that we can address the entire iRAM space? With the addition of two more bits of course, but where would they come from?

Simple...the STATUS register!

We've all heard them referred to as the “bank select” bits but this is just a convention that Microchip decided to use for its “register banking” concept. Bits RP1 and RP0 (Register Page 1 and Register Page 0 respectively) serve as the upper 2 address bits for instructions which directly address the iRAM locations.

So say for instance we wanted to move a value in W to register TRISA, which has iRAM address 0x85 (b'010000101). The instruction could not supply the leading “01” in the address, so these two bits must come from register bits RP0 and RP1. So prior to writing the contents of W to register TRISA, we must first execute these two instructions -


This makes bit RP1 a 0 while making bit RP0 a 1, which gives us the leading “01” in TRISA's address.

Now we want to write to PORTA, which resides at iRAM address 0x05 (b'000000101'). Now the leading two bits must be cleared to access location 0x05 -


This clears both of our RP bits, giving us the two leading zeros at the beginning of our instruction, while the remaining 7 bits come from the instruction itself.

With indirect addressing using the FSR register, we only need 1 more bit. This is because the FSR is an 8 bit register so it can address up to 256 iRAM locations on its own. Its 9th bit comes from bit IRP (Indirect Register Page) in the STATUS register.

With a more conventional processor like the Intel 8051, a mov instruction is 8 bits long, followed by 1 or 2 more bytes that provide the address(es) that the mov instruction is being executed on. With an instruction set of this nature, no iRAM 'banking' is required. But since the PIC is a RISC processor with a single 14 bit instruction word, there will be limits to what can be done and how things must be done, and this is one of them.

If we were to use the FSR to indirectly address register TRISA, we could simply load the FSR with the value of 0x85, load W with the immediate value to write to TRISA, then load the value in W into the INDF register without having to bank select. This is because register FSR is an 8 bit register and can supply 8 of the 9 address bits on its own. However, we must ensure that bit IRP in the STATUS register is clear prior to doing this otherwise we would end up writing to iRAM register address 0x185 instead of 0x085.

So there you have it...PIC 16F register banking explained.
  • Like
Reactions: yugal
Jon Wilder
First release
Last update
5.00 star(s) 1 ratings

More resources from Jon Wilder

EE World Online Articles