Spectacular Butter
New Member
This program takes two 4 bit binary inputs, multiplies them and gives the output in BCD. Since the blanks don't show, i use . to represent blanks for easier reading
-------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity BCDMUL2 is
port( EN : in std_logic;
A, B : in std_logic_vector(3 downto 0);
X : out std_logic_vector(7 downto 0));
end BCDMUL2;
architecture BEHAVIOR of BCDMUL2 is
...signal BIN : std_logic_vector(7 downto 0);
...signal BCD1, BCD0: std_logic_vector(3 downto 0);
begin
...process(EN, A, B)
begin
...BCD1 <= "0000";
...if (EN = '1') then
......BIN <= ("0000" & A) * B;
......for i in 0 to 7 loop
.........if (BIN > "00001001") then
............BIN <= BIN - "00001010";
............BCD1<= BCD1 + "0001";
.........end if;
......end loop;
......BCD0 <= BIN(3 downto 0);
...else
......BCD1 <= "0000";
......BCD0 <= "0000";
...end if;
...X <= BCD1 & BCD0;
...end process;
end BEHAVIOR;
------------------------
I could compile them using Max Plus 2 but when i try to do a waveform simulation, it keeps having input oscillation errors when en = 1. The problem was most probably caused by these statements inside the for loop.
if (BIN > "00001001") then
...BIN <= BIN - "00001010"; (can make assignments this way?)
...BCD1<= BCD1 + "0001";
end if;
I am not sure any VHDL experts out there can figure out the problem. Just giving it a shot. Thanks anyway.
-------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity BCDMUL2 is
port( EN : in std_logic;
A, B : in std_logic_vector(3 downto 0);
X : out std_logic_vector(7 downto 0));
end BCDMUL2;
architecture BEHAVIOR of BCDMUL2 is
...signal BIN : std_logic_vector(7 downto 0);
...signal BCD1, BCD0: std_logic_vector(3 downto 0);
begin
...process(EN, A, B)
begin
...BCD1 <= "0000";
...if (EN = '1') then
......BIN <= ("0000" & A) * B;
......for i in 0 to 7 loop
.........if (BIN > "00001001") then
............BIN <= BIN - "00001010";
............BCD1<= BCD1 + "0001";
.........end if;
......end loop;
......BCD0 <= BIN(3 downto 0);
...else
......BCD1 <= "0000";
......BCD0 <= "0000";
...end if;
...X <= BCD1 & BCD0;
...end process;
end BEHAVIOR;
------------------------
I could compile them using Max Plus 2 but when i try to do a waveform simulation, it keeps having input oscillation errors when en = 1. The problem was most probably caused by these statements inside the for loop.
if (BIN > "00001001") then
...BIN <= BIN - "00001010"; (can make assignments this way?)
...BCD1<= BCD1 + "0001";
end if;
I am not sure any VHDL experts out there can figure out the problem. Just giving it a shot. Thanks anyway.