clock generator circuit

[faraday]

hi friends
I wanna design and simulate a clock generator circuit using Hspice with these specifications:
refrence signal between 880-912MHz with equal steps about 125KHZ that output signal jitter be lower than 20PS(rms) when source has 200mv(p-p) and can drive 3PF load
how can I do that WITHOUT usual methods like (N,N+1) and DSS or sigma-delta?

 

[faraday]

I find this function block diagram for LMX2531 but it is also using (N,N+1) sigma-delta :/