4026 counter

[jas000]

Hi,
I am trying to create a stopwatch as a project, however i am having problems using the 4026 chip. (i'm using a 555 as the pulse)
I have created a small version as a test to work out how the 4026 works. This was a success. I made a stopwatch which counted to 99. Now i am tring to use minutes as well.
I'm trying to use logic gates to tell when the counter gets to 59 seconds, then i'm trying to reset the 4026s to 0 and putting the minute display up 1. However the instead of reseting the 7 segment displays to 0 it freezes them on 59 seconds. I discovered this was because the reset has to be release to actually reset the 4026s. So i used an AND gate to use the pulse from the 555 so it when it got to 59, it resets. This misses a second out: it goes ...58, 59, 01, 02... and not ...58, 59, 00, 01, 02...
Is there an easy way to fix this? Also is there an easier way to make this circuit?
I'm sorry if this is hard to understand: i'm quite new to electronics.
Thanks,
jas000

 

[eblc1388]

I'm trying to use logic gates to tell when the counter gets to 59 seconds, then i'm trying to reset the 4026s to 0 and putting the minute display up 1.

Isn't it a better idea to let the counter counts to 60, then reset it to 00? You won't be able to notice the '60' on the 7-segment display because this state only occurs for several micro seconds before the logic resets the display to 00.

I discovered this was because the reset has to be release to actually reset the 4026s.

In fact, just use logic gate to detect a '6' on the 10th digit and use this to reset the 4026. The reset signal will automatically disappear after the 4026s have reset to '00'.

But with the 4026 where the outputs is already decoded 7-segment signals, it might be a bit difficult for you to detect '6' from the 7-segment output. Just remember, the 'b' segment is off for 5 and 6 and this will be your decode logic rule number one. Rule two is segment 'e' goes high which occurs when digit changes from '5' to '6'.

So the two rules together will give a decoder for '5' to '6'.

 

[tavib]

:lol:
be aware with this simple reset circuit, not work well in all cases, think at a possible reset failed scenario, is very rare but possible.

 

[eblc1388]

:lol:
be aware with this simple reset circuit, not work well in all cases, think at a possible reset failed scenario, is very rare but possible.

You must have spotted something that I've overlooked. Why would the reset not working in rare scenario? Can you tell me a bit more?

I mean, the clock pulse is only once per second and the logic had plenty of time to decode and reset the 4026.

 

[jas000]

If the reset is risky, what's the alternative? Is there another way to reset the 4026s?

Also do you think i should just go: ...59,60,01,02... then?

Thanks,
Jas000

 

[eblc1388]

If the reset is risky, what's the alternative? Is there another way to reset the 4026s?

Also do you think i should just go: ...59,60,01,02... then?

Thanks,
Jas000

Hi Jas000, holds on for just a little bit longer. As far as I know the reset is not risky but let's hear what other posters has to say.

 

[jas000]

reset

As a side question to this thread are the 4026s going out because there arn't very many people selling them.
Thanks,
Jas000

 

[tavib]

:lol:
Is risky because the reset pulse is very short. When the decoder logic will sense 60 for ex, the reset output will go 1, as result the conter bistables and eventually other structures will start the reset process, but if one bistable is faster and other is slower then the faster bistable will be reset, the 60 combination will be change and the output of decoder logic will go in 0, in some defavorable cases before the slower bistable finish the reset process. For fix this potential problem a D flip-flop is inserted between ouptut of decoder logic and the reset input of counter, this flip-flop hold the reset level for half of clock period typical. Also a decoder with a high enough propagation delay can be used in place of flip-flop.

 

[pebe]

:lol:
Is risky because the reset pulse is very short. When the decoder logic will sense 60 for ex, the reset output will go 1, as result the conter bistables and eventually other structures will start the reset process, but if one bistable is faster and other is slower then the faster bistable will be reset, the 60 combination will be change and the output of decoder logic will go in 0, in some defavorable cases before the slower bistable finish the reset process. For fix this potential problem a D flip-flop is inserted between ouptut of decoder logic and the reset input of counter, this flip-flop hold the reset level for half of clock period typical. Also a decoder with a high enough propagation delay can be used in place of flip-flop.

I've experienced this in the past. I have heard it called a 'bit race'. You can probably overcome the effect by slugging the reset pin with a 10nF cap.

 

[FRIED]

I think this is what its about. Not tested
http://www.geocities.com/gpg212/4026secs.GIF
Anyone want to check

 

[eblc1388]

:lol:
Is risky because the reset pulse is very short.

I do agree in general that if you decode the state by external gates at counter bistables output for most counters, it would be risky and a F/F is the proper way to do it.

But not for the case of 4026. It is done at the 7-segment decoded outputs and thus there is already some delay. After the external added decode logic picks this up and remove the reset pulse to the 4026, there is yet another delay. If one is still not satisfied, a 10nF capacitor on the reset pin would give yet more delay as pebe had mentioned.

From the data sheet, the reset pulse propagation to the 7-segment decoded output is typical 300nS and the worst case requirement on min. reset pulse width is only 120nS.

 

[guzzimac]

To get a clean, well behaved reset pulse try this. Detect the "6" condition on the outputs with, say, 6 diodes on the relevant segments with a pullup resistor (6 input AND gate) and connect this to the SET terminal of a D-type flip-flop. Invert the clock pulse and feed this to the RESET terminal of D-type. Connect the Q output to the 4026 reset.

At switch-on the D-type will be reset within one clock pulse and the counter will start. When the 6 is detected the flip-flop will change state and the Q output will go high forcing the counter to 0. Half a second later the inverted clock pulse will reset the D-type so the next rising edge of the clock will count "1".

Instead of a D-type you could use cross-coupled NAND or NOR gates but would need to provide a proper power on reset. Probably safest to do this with the D-type as well just to be sure. Unused inputs to appropriate levels of course.

 

[FRIED]

Did you not look at this?
http://www.geocities.com/gpg212/4026secs.GIF

 

[oliverb]

I am looking to build a digital clock using 7 seg LED diplays. I have built and tested the following on breadboard using 4026BE ICs.

All displays seem to reset OK.

The Hours reset at 24 and the mins and seconds at 60.

The only way I could see to reset at 24 was using a 2 input Nor and a 4 input Nor gate. Pin 5 of the 4 I/P Nor is connected to the 2 OP of the Tens digit (goes low when couinter >2) the other 3 are connected to the Units digit display OP.

I have searched the Net and cannot find an example cct showing this.

Is this the easiest way or does anyone know of a better way of doing this?

Brett.