CPLD (Xilinx) programming tutorial - Electronic Circuits Projects Diagrams Free

petrv · 15th May 2008, 07:05 AM

How to start with programmable logic.
1. You'll need a PC with a parallel port (true parallel port, no USB adapters)
2. Download and install the Xilinx ISE Webpack from www.xilinx.com
3. get/buy/build the Xilinx Parallel cable III programming adapter
4. get a Xilinx CPLD, for example XC9572 in PLCC-44 package
you can also buy a PLCC-44 to DIP adapter (e.g. Aries, from DigiKey) and
use breadboard.

When programming a CPLD (or FPGA) you don't create a program but description of the logic that implements the desired functionality, usually using a hardware description language. I will use VHDL in the example.

Example #1: Implement a synchronous 4-bit counter with asynchronous reset and synchronous load (a little like a simplified 74161) signals active in '1', clock at rising edge.

Create a new project, select directory and top level source HDL, Next>
Select device (XC9572) and package (PC44) preferred language VHDL.
Then you can use the wizard to create a new source (mycounter.vhd)
and implement the logic - copy the VHDL code from below:

Code:

-- includes (common useful libraries)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- tutorial: 4 bit counter design
entity Mycounter is
    Port ( reset 	: in  std_logic;		-- asynchronous reset
           clk 	: in  std_logic;     -- master clock input, active rising edge
           load 	: in  std_logic;     -- synchronous load enable
           data 	: in  std_logic_vector (3 downto 0); -- data to load if load is '1'
           output : out  std_logic_vector (3 downto 0)); -- output of the counter
end Mycounter;

architecture rtl of Mycounter is
	
	-- VHDL does not allow using output signals as input so I need this helper signal
	signal	myout: std_logic_vector(3 downto 0);

begin
	
	-- send out helper signal to the output pins
	output <= myout;
	
	-- this is the output signal
	cntr: process (reset, clk)
	begin
		if	reset = '1' then
			myout <= "0000"; -- reset active ...
		elsif rising_edge(clk) then -- no reset, so wait for rising edge of the clock
			if load = '1' then
				myout <= data; -- load was active so copy input data to the output
			else
				myout <= myout + 1; -- load was not active so count ....
			end if;
		end if;
	end process cntr; --- that's all
	
end rtl;

Then you can run the implementation (Menu Process/Run) and if everything is ok, a programming file for the CPLD is created. The only problem is we don't know which pins are the signals load, data ....

So let's add another file - User constraints file (.ucf) where we force the implementation to use specific pins for our signals
Click on the left side Create new source and select implementation constraints, name it MyCounter.ucf. Here is my selection of pins:

Code:

NET "clk"        LOC = "P5" ;
NET "data<0>"    LOC = "P1"  ;
NET "data<1>"    LOC = "P2"  ;
NET "data<2>"    LOC = "P3"  ;
NET "data<3>"    LOC = "P4"  ;
NET "load"       LOC = "P44"  ;
NET "output<0>"  LOC = "P12"  ;
NET "output<1>"  LOC = "P11"  ;
NET "output<2>"  LOC = "P9"  ;
NET "output<3>"  LOC = "P8"  ;
NET "reset"      LOC = "P39" ;

There are specialized pins optimized for clock input (GCK) and for global reset (GSR) so I used them, other pins I just chose what was conveninent ....
Now it is time to run implementation again and them to program the CPLD.

To program the programming file into the CPLD connect the JTAG pins of the CPLD to the programming adapter, power the CPLD and adapter (5V for XC9500 family and 3.3V for XC9500XL family). Expand the Generate Programming File and select Configure Device (iMPACT). Use the default options.
After programing the CPLD you can connect it on a breadboard and check that it performs the designed function - a 4-bit binary counter

Enjoy.

Petr

15th May 2008, 07:05 AM	(permalink)
petrv Experienced Member	CPLD (Xilinx) programming tutorial How to start with programmable logic. 1. You'll need a PC with a parallel port (true parallel port, no USB adapters) 2. Download and install the Xilinx ISE Webpack from www.xilinx.com 3. get/buy/build the Xilinx Parallel cable III programming adapter 4. get a Xilinx CPLD, for example XC9572 in PLCC-44 package you can also buy a PLCC-44 to DIP adapter (e.g. Aries, from DigiKey) and use breadboard. When programming a CPLD (or FPGA) you don't create a program but description of the logic that implements the desired functionality, usually using a hardware description language. I will use VHDL in the example. Example #1: Implement a synchronous 4-bit counter with asynchronous reset and synchronous load (a little like a simplified 74161) signals active in '1', clock at rising edge. Create a new project, select directory and top level source HDL, Next> Select device (XC9572) and package (PC44) preferred language VHDL. Then you can use the wizard to create a new source (mycounter.vhd) and implement the logic - copy the VHDL code from below: Code: -- includes (common useful libraries) library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- tutorial: 4 bit counter design entity Mycounter is Port ( reset : in std_logic; -- asynchronous reset clk : in std_logic; -- master clock input, active rising edge load : in std_logic; -- synchronous load enable data : in std_logic_vector (3 downto 0); -- data to load if load is '1' output : out std_logic_vector (3 downto 0)); -- output of the counter end Mycounter; architecture rtl of Mycounter is -- VHDL does not allow using output signals as input so I need this helper signal signal myout: std_logic_vector(3 downto 0); begin -- send out helper signal to the output pins output <= myout; -- this is the output signal cntr: process (reset, clk) begin if reset = '1' then myout <= "0000"; -- reset active ... elsif rising_edge(clk) then -- no reset, so wait for rising edge of the clock if load = '1' then myout <= data; -- load was active so copy input data to the output else myout <= myout + 1; -- load was not active so count .... end if; end if; end process cntr; --- that's all end rtl; Then you can run the implementation (Menu Process/Run) and if everything is ok, a programming file for the CPLD is created. The only problem is we don't know which pins are the signals load, data .... So let's add another file - User constraints file (.ucf) where we force the implementation to use specific pins for our signals Click on the left side Create new source and select implementation constraints, name it MyCounter.ucf. Here is my selection of pins: Code: NET "clk" LOC = "P5" ; NET "data<0>" LOC = "P1" ; NET "data<1>" LOC = "P2" ; NET "data<2>" LOC = "P3" ; NET "data<3>" LOC = "P4" ; NET "load" LOC = "P44" ; NET "output<0>" LOC = "P12" ; NET "output<1>" LOC = "P11" ; NET "output<2>" LOC = "P9" ; NET "output<3>" LOC = "P8" ; NET "reset" LOC = "P39" ; There are specialized pins optimized for clock input (GCK) and for global reset (GSR) so I used them, other pins I just chose what was conveninent .... Now it is time to run implementation again and them to program the CPLD. To program the programming file into the CPLD connect the JTAG pins of the CPLD to the programming adapter, power the CPLD and adapter (5V for XC9500 family and 3.3V for XC9500XL family). Expand the Generate Programming File and select Configure Device (iMPACT). Use the default options. After programing the CPLD you can connect it on a breadboard and check that it performs the designed function - a 4-bit binary counter Enjoy. Petr

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