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Yet another mosfet question

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drkidd22

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I have the circuits below. Basically everything is the same except the location of the load resistors R1 and R3.
I was expecting to see the same results for both setups, but I don't. I assume this has to do with the Vgs voltage but it doesn't come clear to me what the issue is with the circuit on the right shown in blue, it's offset or something.
pmosfet.PNG
 

MikeMl

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The one on the left is an inverting common source amplifier, where Vd swings from very close to gnd all the way to +10V. The one on the right is a non-inverting source follower, where its source is always Vgs more positive than its gate.

Plot the voltage at the drain of M1 and the source of M2.
 

drkidd22

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The one on the left is an inverting common source amplifier, where Vd swings from very close to gnd all the way to +10V. The one on the right is a non-inverting source follower, where its source is always Vgs more positive than its gate.

Plot the voltage at the drain of M1 and the source of M2.
Ok got it. But why is the source of M2 riding at Vgs? What causes this?
The source of M2 is riding on 3.4V so (10-3.4) * 100 = 66mA I think I understand that, but not where this 3.4 riding voltage comes from.

positiveDiodeClamp2.PNG
 

audioguru

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The source voltage of the P-channel source follower Mosfet is about 3.4V more positive than the gate voltage when it is conducting, so when the gate is +10V the source is +10V and when the gate is 0V then the source is +6.6V.
 

MikeMl

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Ok got it. But why is the source of M2 riding at Vgs? What causes this?
In order for the pMOS to begin conducting current, the voltage on the gate V(g) has to be more negative than its source V(s) by more than Vth. Look here:
ps.png

I purposely sweep V(g) from 12V to -4V to see over what region V(s) "follows" the gate voltage. Obviously, the source voltage V(s) cannot go more positive than 10V (because of V1), nor can it go below 0V (because the drain is at gnd=0V).

Note that for my chosen PMOS which has a Vth of -1.6V, V(g) has to be only ~8.4V to allow the source to rise to 10V (Id=Is=0). Even though V(g) rises to 12V, the source cannot "follow".

When V(g) =0V, V(s) is still ~2V. We have to get V(g) to -2V in order for V(s) to be 0V, but as V(g) gets more negative, then V(s) cannot "follow" any lower...
 
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drkidd22

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So I did another circuit shown below. But basically V3 will be a control line to enable/disable M2 to prevent current flow. But it doesn't matter if I have V3 low or high I always get current through flow L1. Now if I connect the source of M2 to L1 it works as expected. Why is this? Because the source is not held at a constant voltage?
InductiveLoad.PNG
 

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MikeMl

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The only way you could saturate M2 (turn on fully) is if the gate is held at ~-5V. Its threshold is -2.4V. If you hold its gate at 0V, then the lowest its source will pull is slightly more more positive than the threshold voltage, so about +2.5V, so the problem is not that you cannot shut the current through the relay off, but that you can never turn it on fully.

Look at the following: I switch M2 and M4 through all four possible combinations. Note that V(r) never goes close to 0V! V(m2_gate) would have to go to <-2.5V to allow M2 to fully turn on... Note that the relay current is (12-2.5)/12 = ~0.8A

drk.png

Do you want V3 to enable and disable M4? If so, there is another way of doing it...
 

MikeMl

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Try this. Relay is driven only if V1 is high and V3 is low. Now V(r) is as low as determined by M4 Ron.

drk1.png
 

drkidd22

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Ok got it thanks. So this way I wouldn't get the gate offset voltage and be able to get almost all of the current.
Thanks for your help.
 
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