...
For example, I would like to try using an 8.388608 Hz crystal with 4xPLL, a 24 bit phase accumulator, and a 20 cycle DDS loop to produce FDDS = 419,430.4 Hz with 1/40th Hz frequency resolution (FRES = 419430.4/2^24 = 0.025 Hz). That would make it relatively easy to maintain a 'display' variable with a value of frequency*10 (like 2541 for 254.1 Hz or 15000 for 1500.0 Hz). Bumping the frequency output up or down by 1, 2, 5, or 10 Hz would simply involve adding or subtracting integer 10, 20, 50, or 100 from the display variable and adding or subtracting integer 10*4, 20*4, 50*4, or 100*4 from the DDS tuning word (phase offset) variable. What do you think?
...