XOR Gate Chip SN74LS86

[Strablan]

Hi All

Im trying to get the above chip to work but without any luck, probably something simple that Im missing. Looking at the data sheet for the chip I have all the pins sorted, 7 to ground, 5 volts to 14 and using pins 1 & 2 for inputs. However I can't get any change out of pin 3 (output) no matter what I do with pins 1 & 2. From what I understand if either of the inputs goes high, pin 3 will go high otherwise remain low. What voltage does either of the input pins require to be classed as high ? Is there a straight forward way to test the chip.

Many thanks for any help

:?

 

[williB]

Hi All

Im trying to get the above chip to work but without any luck, probably something simple that Im missing. Looking at the data sheet for the chip I have all the pins sorted, 7 to ground, 5 volts to 14 and using pins 1 & 2 for inputs. However I can't get any change out of pin 3 (output) no matter what I do with pins 1 & 2. From what I understand if either of the inputs goes high, pin 3 will go high otherwise remain low. What voltage does either of the input pins require to be classed as high ? Is there a straight forward way to test the chip.

Many thanks for any help

:?

yes either input can go high but not both...
did you try grounding one of the inputs and let the other one float high

 

[Strablan]

Thanks for your reply

did you try grounding one of the inputs and let the other one float high

I tried that and got 0 volts from pin 3, then let both float and got 0.2 volts from pin 3. From further reading I gather when the output pin goes high I should get 5 volts, could the chip be damaged ?

 

[Sebi]

The logic inputs need always definite levels. Connect one input to GND, another to +5V. Floating inputs most of case high level.

 

[williB]

Thanks for your reply

did you try grounding one of the inputs and let the other one float high

I tried that and got 0 volts from pin 3, then let both float and got 0.2 volts from pin 3. From further reading I gather when the output pin goes high I should get 5 volts, could the chip be damaged ?

you have three other gates on that chip.. try another one..

 

[Strablan]

I may have the answer : Upon reviewing the data sheet again I see the output low voltage is 8mA and output high voltage is -0.4mA. Does this explain the readings I was getting, if so apologies for not spotting this sooner ?

 

[Roff]

I may have the answer : Upon reviewing the data sheet again I see the output low voltage is 8mA and output high voltage is -0.4mA. Does this explain the readings I was getting, if so apologies for not spotting this sooner ?

No, those are not voltages, those are the currents that an output can sink (output low) or source (output high) respectively, and still maintain a valid logic level. If you really have pin 14 to +5V and pin 7 to GND, and you connect one of the inputs to +5V and the other to GND, the output should go high (around 4V). If you connect both inputs to GND, or both inputs to +5V, the output should go low (around 0.2V). The reason for the current specs you mentioned is that TTL circuits draw current on their inputs, so there is a limit to how many TTL loads you can drive with a given output and still maintain valid logic levels.

 

[Strablan]

Have tried again with this chip and still the same result, I am seriously begining to think I may have inadvertantly damaged it somehow, possibly burnt it out. I will take a trip to the store tomorrow and purchase some replacements and try again.

Many thanks for all the help given.

I will post my progress with the new chips in due course

 

[Strablan]

Success! The new chips worked perfectly. Many thanks again to everyone who answered my query.

This site rocks

 

[williB]

lol Yes It indeed does..

 

[Dean Huster]

As a bit of further info on an XOR, they can be cascaded as you would an AND or OR gate for more inputs, but you lose the "exclusivity" when you do this. The logic becomes, "if you have an odd number of inputs that are HIGH and the rest are LOW, the output will be HIGH; in all other cases, the output will be low." This is great logic if you're using the circuit for things like parity generation and parity checking.

But the formal definition of an XOR gate is more like, "if one and ONLY one input goes HIGH and all other inputs are LOW, the output will go HIGH; in all other cases, the output will be LOW." That's a lot tougher to achieve for multiple-input uses.

Ever notice that an XOR or XNOR gate is only available with two inputs while the AND and OR gates often are available with 3, 4 or even 8 inputs?

Dean

 

[Strablan]

Thanks for that Dean, I will keep that in mind