I read the datasheet because Pommie doubted my solution. I just had to check if my "guess" was right. Well, Ian already said I was right.. and he knows PICs. The datasheet says:
It is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte to
begin shifting to the RSR register. On the detection of
the Stop bit of the third byte,
if the RCREG register is
still full, the Overrun Error bit, OERR (RCSTA<1>), will
be set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in soft-
ware. This is done by resetting the receive logic (CREN
is cleared and then set).
If bit OERR is set, transfers
from the RSR register to the RCREG register are inhib-
ited and no further data will be received. It is, therefore,
essential to clear error bit OERR if it is set.
So the problem is exactly what I suspected. If you (Ritesh) would just read the datasheet.. even a little. You might learn something.
https://www.electro-tech-online.com/custompdfs/2013/07/39582b.pdf
Of course delays are not a very good solution. Better solution is to check the error-bit and clear it if it is set. Or better yet, read the data often enough so that there is no Overrun Error happening.