breakshift
Member
I'm going to build a variable Wien Bridge oscillator with a FET based AGC circuit to minimise the distortion, based on the circuit in Figure 12 here:
**broken link removed**
I understand how the Wien Bridge part works, and I understand how the FET element varies the gain according to the output signal amplitude. The negative feedback loop should be designed to give a gain as close to 3 as possible; less than 3 causes oscillations to stop and more than 3 causes increasing distortion. But how is the AGC circuit designed to hit the magic 3 bang-on? I understand perfectly the mechanism by which the FET device stabilises the output voltage by varying the gain; how the circuit, at start-up, builds up the output voltage which in turn causes the FET to reduce the gain and cause the output voltage to settle at a particular amplitude. But how do you work out the output voltage (and the gain) that the AGC is trying to achieve? How do you know where this equilibrium is going to be in terms of gain and/or output amplitude?
I understand how the circuit in Fig 12 above sets the gain to have a minimum and a maximum value, creating a small range that the FET can vary through. But again how do you know your AGC is going to hit the magic gain of 3?
Is it the case that by adding the FET into the circuit, it will simply reduce the gain slightly (because it adds some small resistance to the feedback loop) from what the gain would be with the FET removed? So you design your feedback network to be just above 3, and then add the FET to drop the gain slightly.
Basically how would you design this circuit to maintain a constant gain of 3?
**broken link removed**
I understand how the Wien Bridge part works, and I understand how the FET element varies the gain according to the output signal amplitude. The negative feedback loop should be designed to give a gain as close to 3 as possible; less than 3 causes oscillations to stop and more than 3 causes increasing distortion. But how is the AGC circuit designed to hit the magic 3 bang-on? I understand perfectly the mechanism by which the FET device stabilises the output voltage by varying the gain; how the circuit, at start-up, builds up the output voltage which in turn causes the FET to reduce the gain and cause the output voltage to settle at a particular amplitude. But how do you work out the output voltage (and the gain) that the AGC is trying to achieve? How do you know where this equilibrium is going to be in terms of gain and/or output amplitude?
I understand how the circuit in Fig 12 above sets the gain to have a minimum and a maximum value, creating a small range that the FET can vary through. But again how do you know your AGC is going to hit the magic gain of 3?
Is it the case that by adding the FET into the circuit, it will simply reduce the gain slightly (because it adds some small resistance to the feedback loop) from what the gain would be with the FET removed? So you design your feedback network to be just above 3, and then add the FET to drop the gain slightly.
Basically how would you design this circuit to maintain a constant gain of 3?
