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Why is recomended land pattern recomending such small thermal pad size?

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Flyback

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Hello
The 25th page of the below app note shows the land pattern of an offline linear LED driver IC.
The FETs in this package operate in the linear region.
Why is the land pattern showing a central thermal pad of dimension just 3mm by 3mm?
There is room there to make it 4mm by 4mm and still have plenty of clearance away from the actual outer pads. The solder mask could still be 3mm by 3mm so that the IC “locates” in the centre of the land pattern during the reflow soldering process.
So why have the manufacturers not recommended a bigger thermal pad for this IC?

DT3001 LED driver IC:
http://www.seoulsemicon.com/_upload/Goods_Spec/Acrich2-Applicationnote.pdf
 

Flyback

Well-Known Member
Thanks, great article.
Just noting the page 3 says "do not cover the vias with solder mask which causes excessive voiding"

...dont they mean "solder resist"?...they are talking about vias in pads of QFN.s
..Surely you want solder mask over a QFN pad....even when it has thermal vias in it?
 

RadioRon

Well-Known Member
It doesn't need to be larger than 3x3 mm because they rely on in-pad vias to take the heat to other layers. The thermal performance without these in-pad vias would be hopelessly bad whether it was 3x3 or 4x4.

They are talking about solder mask, the green stuff. No, you don't want solder mask over an in-pad via because, as they say, it tends to hold the IC up too high. The industry deals with the problem of solder leaking out those open vias by either plugging them during the pcb fab process (Plugged via or button print via, or plugged and plated-over) or by making them so small that they really don't leak enough to worry about (ie. less than .008 inches dia). They usually don't recommend simply putting solder mask over the via on both sides (so-called Tenting) because during reflow these vias tend to explode in a very tiny way when the internal trapped moisture boils. Its ok to tent the via only on the IC side if you can tolerate the IC sitting high on the pad, such as when doing a prototype. For one-off and prototypes, just letting some solder leak out the other side is tolerable, so no need to do anything but make the in-pad vias narrow.
 

Flyback

Well-Known Member
It doesn't need to be larger than 3x3 mm because they rely on in-pad vias to take the heat to other layers. The thermal performance without these in-pad vias would be hopelessly bad whether it was 3x3 or 4x4.
Thanks, though if we make it 4x4mm then we can put more thermal vias in this pad, which is better?
Regarding having solder resist under the IC, the IC (DT3007) is 6mm x 6mm, -so do you think that there should be absolutely no solder resist under this whole 6x6 area at all?
 

jpanhalt

Well-Known Member
Most Helpful Member
Regarding having solder resist under the IC, the IC (DT3007) is 6mm x 6mm, -so do you think that there should be absolutely no solder resist under this whole 6x6 area at all?
I would follow the manufacturer's recommendation. I have never used either chip, so my opinion about those specific products is irrelevant.

Some manufacturers recommend solder-mask defined pads; others recommend against it. If the manufacturer says no solder-mask under a specific area, that is usually because the chip needs good thermal and/or solder contact. Solder mask where it is not supposed to be can raise a chip enough that solder contact with areas it is supposed to contact may not happen reliably. If one adds more solder paste to avoid that, then you can get other problems as described in the TI document -- namely more bridging or failed solder joints by capillary action of vias (pages 4-5, loc. cit.).
 

Flyback

Well-Known Member
I would follow the manufacturer's recommendation.
Thanks, though Seoul dont say whether or not there shold be no solder resist under the 6x6 area of the IC. -Or do you mean the PCB assembler when you say "manufacturer"?
If we are going to have any solder resist under the IC, then we may as well do a solder-resist-defined-pad which is 3x3 but in a 4x4 total copper area. Do you agree?
 

Flyback

Well-Known Member
Our PCB layout engineer has placed five thermal vias of diameter 0.65mm in the thermal pad of our DT3001 IC. (as in the jpeg attached).
he seems to have just used five square PTH vias, which as you can see , dont fit together very well and hence there is solder resist between them. Is this bad?
So has got solder resist over the thermal pad. (as attached)
Surely 0.65mm is way too big for a thermal via in such a small thermal pad?
(he has made the thermal pad 3mm x 3mm)
 

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ronsimpson

Well-Known Member
Most Helpful Member
I don't like your middle pad. Changed it to a square. (pink)
Then added more copper under the part, on all layers. Bring out the copper on the top layer to close to the pads. On the other layers it could come out much bigger.
On the bottom right corner; this is how I would do all four corners. (red)
upload_2017-8-7_6-23-56.png
 

Flyback

Well-Known Member
Thanks RonSimpson,
That looks like a really good thermal pad design. The DT3001 IC is an offline LED driver IC, and there is mains voltage going into its pins, I just wondered if the clearance from centre pad to outer pads was being kept at 1.025mm because of the voltage? The DT3001 datasheet doesn’t say which pin (if any) that the centre thermal pad is connected to…but implies that it should be left floating.

Though if there is solder resist over the outer edges of the centre pad then that eases the clearance concern?

Also, is there any concern that having any solder resist under the 6x6 area of the IC might hold it up off the centre thermal pad and prevent effective soldering to the centre thermal pad?
 

ronsimpson

Well-Known Member
Most Helpful Member
I think the solder past is thicker than the solder mask. (resist)
If there is high voltage on a pin then keep the copper back away from the pad.
If a part is hot, I use very thick traces. Traces as thick as the pad, to help pull heat out away from the part.
 

Flyback

Well-Known Member
Thanks, and you would agree that 0.65mm diameter is way too big for a thermal via, as in the above?
 

DerStrom8

Super Moderator
Most Helpful Member
...dont they mean "solder resist"?...they are talking about vias in pads of QFN.s
..Surely you want solder mask over a QFN pad....even when it has thermal vias in it?
Not sure I understand here. Solder mask = solder resist. It masks the areas where you don't want solder to go. Are you thinking solder paste? The paste mask is completely different from the solder mask.
 
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