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Why does step-up sepic with 10uf sepic capacitor go unstable?

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Flyback

Well-Known Member
Hello
Why does the SEPIC converter (5V-15V) with a SEPIC capacitor value of 10uF go unstable?
The exact same sepic converter, but using a 33uF Sepic capacitor is perfectly stable.
Why is the one with the 10uF capacitor unstable?
Also, a sepic converter which steps down from 15V to 5V and uses a 10uF capacitor is perfectly stable.
Why is the 5-15V sepic converter unstable, and the other two are stable?
The LTspice simulations are attached.
Each of these three sepic converters have the follwing common features…
-exact same (uncoupled) sepic inductor values
-exact same switching frequency
-exact same feedback compensation components (except for upper output divider
resistor, slope comp and sense resistor)
-All have load power of 7.5W
-All are current mode
So, what makes the step-up sepic, with a 10uF sepic capacitor, go unstable?

LTspice simulations can be run by saving .txt file as .asc , then open in ltspice (free sim), and hit running man icon.
 

Attachments

  • Sepic 5-15v 10uF.txt
    5.2 KB · Views: 180
  • Sepic 5-15v 33uF.txt
    5.2 KB · Views: 167
  • Sepic 15-5v 10uF.txt
    4.7 KB · Views: 152
  • Sepic 5-15v 10uF.pdf
    15.9 KB · Views: 185
Hi there Flyback,

Can you post the circuit as a schematic?

Boost circuits are very tricky because they have a control mechanism that is opposite to most other control mechanisms that involve digital control over an analog process. That is, a switch that can only turn on or off that has to control an analog output, but the relationship between the switch and the output is opposite to that of most other control schemes, and this causes various problems.

For example, for the buck circuit when we want a higher output voltage we simply turn the switch 'on', or just keep it on longer, and during that SAME time period the output climbs higher. Tor the boost circuit the output goes higher by keeping the switch 'on' for a longer time period but during that same time period the output is not receiving any new energy so the output actually falls. This results is a problem with phase because when the control circuit sees the output too low it actually has to allow the output to go even lower so the intermediate stage can gain more energy from the input source. This action is said to generate a right half plane zero which causes instability, but the exact analysis of this is quite complicated and very abstract from the actual circuit.
So the circuit is almost like a tuned circuit where the component values could cause instability. One of the other things that comes up is the capacitor ESR value. If the ESR value is changed to a lower value it could cause the circuit to go unstable.

But it would be nice to see a schematic of the actual circuit you are looking at.
 
Last edited:
..Thanks MrAl, the schematic is in the top post, theres three text file sims, then the pdf.
I need to find the RHPZ frequency for a sepic.
 
I believe you can upload .asc files directly.
 
Hi again,

Oh ok i guess i missed that .pdf as i thought they were all text files.

This is quite a complicated circuit really to do a full analysis on. The extra 10uf and extra inductor makes it more complicated than a regular boost converter. Combined with the feedback network, it makes for a huge equation. Roughly speaking, every capacitor adds one more order to the equation, as does every inductor, so 5 caps and 2 inductors would probably mean a 7th order equation.

I would suggest that you start with a much simpler boost converter and go from there unless you have a good reason for doing this one first. But if you've never looked at this kind of problem before it would be best if you examined a simpler circuit first, then continued with this one if needed.

Also, the analysis and/or simulation is truly moot if the components do not have any series resistance. We must know these values in order to get anything that resembles real life operation. As i was saying in a previous post, for these kinds of converters the ESR values are much more important and can make or break a design. So that means we need to know the ESR of every inductor and capacitor in the power stages at least, although the compensation network ESR values are of less importance.
 
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