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Why does phase shift full bridge simulation have dc bias level in magnetising current?

Discussion in 'Circuit Simulation & PCB Design' started by Flyback, Jan 22, 2015.

  1. Flyback

    Flyback Well-Known Member

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    Hello,
    Here are simulations ( in the free LTspice) of a Full Bridge SMPS, and a Phase Shift Full Bridge SMPS.
    Why is it that the phase shift full bridge smps has a dc bias level in its magnetising current? (you can see the magnetising current by pasting the supplied expression in the simulation schematic into the waveform window, using “add trace”…just right click in the top bit of the waveform window and paste the expression into the window that pops up)
    The plain full bridge has no dc bias level in its magnetising current. (This is what you would expect for both topologies)
     

    Attached Files:

  2. Flyback

    Flyback Well-Known Member

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    sorry, had to edit something
     
    Last edited: Jan 22, 2015

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