Look at this simulation.
P1 and P2 are the inputs to the IR2110
I would say that is the intention, so that both High and Low FET pairs are not ON at the same time at the switching edge.Are they to add a period of dead time between switching the push pull output FETs,
hi,Thanks again Eric, what i don't get, if that's their intention, is how it would work. Surely if it worked as a delay it's delaying both the same amount of time, so potentially they could still switch on at the same time. Wouldn't one have to be a different value to the other?
Oops! so you were.I was asking about C1 and C2, but thanks for the info re gate capacitance. I am also aware that with paralleled devices the driver has to work twice as hard, I believe?
Eurika- that is probably the main operational reason for the Rs and Cs: to protect the circuit during power-up when, initially, the signal may not be present.By using the second gate input on the 74HCT132, it would be possible to inhibit the clocking source to the 7474 during power up.