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Voltage Monitor - SPI Pullup?

wuchy143

Member
Hi All,

I am modifying a voltage monitor matrix where they have used chip select on the part coupled with the SDATA lines to create each VMON chip to be addressable by the FPGA. I didn't write the VHDL but there is some type of state machine in the FPGA that "takes care" of this. Just want to give some history as to what I am trying to do.

So, essentially I am adding in another VMON chip into the matrix and I'm a little confused by the pullup resistor used and want to see if someone knows why? I know that it is good to either pullup/pulldown the mosi line due to it not always being asserted and could be floating. SPI is a totem pole so I didn't think we need the pullup/pulldowns right?

My main question is why when 3 chips share a dataline they don't need a pull up and when there is only a single chip a pullup is needed?

I made a visio so we can chat about it a little more easily. I am thinking it may have to do with how SPI works which I haven't had a ton of experience with. Maybe something with loading or whatever when you only have a single chip on the data line. Anyway, any light you all can please shine on this would be very helpful.

Thank you.
 

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