verilog question

[samcheetah]

is it legal to do the following in verilog?

module and_or( out, in1, in2, ctrl );

output out;
input in1, in2, ctrl;

reg out;

always @(in1 or in2 or ctrl)
begin

	if(ctrl)
		and (out, in1, in2);
	else
		or (out, in1, in2);
end

endmodule

in1 and in2 are two inputs that are ANDed if ctrl is high and if it is low then the inputs are ORed. the problem is with the AND and OR statements. if i replace them with data-flow level operators (& and |) the program compiles perfectly. but i want to do it in the gate-level. is this legal to use AND and OR expressions in if statements like this.

and by the way this is related to homework. but this piece of code isnt my homework (i just wish they gave something simple as this :lol: ). the actual code is something else but the problem is the same.

 

[fsahmed]

Behavioural modelling caters for registers only & will not accomodate in1 & in2 as inputs of the AND or OR gates, these being nets, not registers. Otherwise, the use of gate primitives is legal though maybe a few ocmpilers may not support it.