jhanus
New Member
Hello,
I just bought a USB drive and although I'm satisfied with it's performance 33MB/s read and 16MB/s write, I just had an idea, since DDR2 is very cheap now and DDR3 soon will replace DDR2, to build a bridge between DDR2 and USB with PIC.
Point of this would be to max out USB 2.0 High Speed standard of 480Mb/s(60MB/s) and future USB 3.0, 4.8 Gbit/s (600 MB/s) with DDR2.
Maxing out could be easily done even with DDR1, but since it's out of production and DDR2 is more cheap it is a obvious choice.
Device could use different memory brands because it will be under clocked anyway(frequency and latency).
DDR1
DDR2
And since USB drives use FLASH memory which is 'good' for sequential write/read it totally fails in random access, which will only get more noticeable in larger capacities, when data is segmented.
Projects:
- NEGATIVE:
A negative side would be it needs a battery/accumulator.
- POSITIVE:
Fast as interface allows it, 'theoretically no limits'.
Longer life cycle, FLASH is based on EEPROM, and it's write cycle limited.
Obviously PIC(at least 16F/18F) doesn't have the power to transport so much information but a memory controller for DDR2 should exist, but I can't find any, so help me to find one(more)!
A similar 'project', built around Xilinx Spartan 3.
What are your opinions?
I just bought a USB drive and although I'm satisfied with it's performance 33MB/s read and 16MB/s write, I just had an idea, since DDR2 is very cheap now and DDR3 soon will replace DDR2, to build a bridge between DDR2 and USB with PIC.
Point of this would be to max out USB 2.0 High Speed standard of 480Mb/s(60MB/s) and future USB 3.0, 4.8 Gbit/s (600 MB/s) with DDR2.
Maxing out could be easily done even with DDR1, but since it's out of production and DDR2 is more cheap it is a obvious choice.
Device could use different memory brands because it will be under clocked anyway(frequency and latency).
DDR1
Code:
Standard name Memory clock Cycle time I/O Bus clock Data transfers per second JEDEC standard VDDQ voltage Peak transfer rate
DDR-200 100 MHz 10 ns [1] 100 MHz 200 Million 2.5v +/- 0.2v PC-1600 1600MB/s
DDR-266 133 MHz 7.5 ns 133 MHz 266 Million 2.5v +/- 0.2v PC-2100 2100 MB/s
DDR-333 166 MHz 6 ns 166 MHz 333 Million 2.5v +/- 0.2v PC-2700 2700 MB/s
DDR-400 200 MHz 5 ns 200 MHz 400 Million 2.6v +/- 0.1v PC-3200 3200 MB/sDDR2
Code:
Standard name Memory clock Cycle time I/O Bus clock Data transfers per second Peak transfer rate
DDR2-400 100 MHz 10 ns 200 MHz 400 Million PC2-3200 3200 MB/s
DDR2-533 133 MHz 7.5 ns 266 MHz 533 Million PC2-4200 4266 MB/s
DDR2-667 166 MHz 6 ns 333 MHz 667 Million PC2-5300 5333 MB/s
DDR2-800 200 MHz 5 ns 400 MHz 800 Million PC2-6400 6400 MB/s
DDR2-1066 266 MHz 3.75 ns 533 MHz 1066 Million PC2-8500 8533 MB/sAnd since USB drives use FLASH memory which is 'good' for sequential write/read it totally fails in random access, which will only get more noticeable in larger capacities, when data is segmented.
Projects:
- NEGATIVE:
A negative side would be it needs a battery/accumulator.
- POSITIVE:
Fast as interface allows it, 'theoretically no limits'.
Longer life cycle, FLASH is based on EEPROM, and it's write cycle limited.
Obviously PIC(at least 16F/18F) doesn't have the power to transport so much information but a memory controller for DDR2 should exist, but I can't find any, so help me to find one(more)!
A similar 'project', built around Xilinx Spartan 3.
What are your opinions?