Urgent help for wide swing cascode current mirror

URGENT HELP PLEASE!!!
I want to design a wide swing cascode current mirror (question-left) and in order to apply Iref, I have designed a PTAT and applied it to M7 and M9 (design). Iref must be 50uA and the diagram of output should be like the diagram in picture (question-right).
The problem is that, When I do simulation, I have I=0 for V<0.6 and it gradually increases (pic3), while it shouldn't be like this. I don't know in which part I'm designing wrong and I don't know how to solve it. would you please help me urgently????
Thanks in advance.

The generic FETs in LTspice don't work well. Have you defined/included specific models for N49, P50 etc?

Yes, I've used TCMS technology for 0.35 and 0.25u and in the attached file, it's the specs

I've also done a second design. and here are the results which is not acceptable yet... Don't know what to do...

Which voltage are you varying in result2? V1, V2, or V3? Why not combine V1 and V2 into a single source?

I tried. The result was not desirable. I think there's something very wrong with my design from the very beginning...
I was going the analyzes based on V2. Btw, I will start it from scratch again.

There is no reason that combining V1 and V2 shouldn't work unless SPICE is getting fussy and possibly giving bad results. Do you have other versions of SPICE that you can check the simulation against?