type 2 Compensator Circuit Simulation

[garimella]

I was referring to the following article in the link www.21dianyuan.com/home/download.php?action=download&id=67736
Fig.7 Shows type2 circuit. My doubt are as follows
1.I tried simulating the same circuit standalone. But the output always saturates for both AC and DC signals. The values selected are R1= 30 ohms. Rbias is open. R2=10K, C1=1uf, c2= 0.1uf. Vref was made 0V and changed to other values, still output saturates. Where am I going wrong?

2. What is the relation between vout and vin, vref? Transfer function mentioned in the article does not include vref.

 

[MikeMl]

The type 2 circuit is an integrator, so even with identical Vin and Vref, the input offset of the opamp will be integrated, eventually railing the output of the opamp.

In order to simulate the open-loop frequency response of this circuit, you will have "close the loop" for DC, or use an "ideal" opamp which has zero offset referred to its inputs.

The simulation shows an ideal, zero-offset amplifier from the LTSpice library. I make the offset -2mV (green), -1mV, o, +1mV, and finally +2mV (violet). If I force V(out) to zero at the beginning, the simulation shows how fast the amplifier rails just integrating the offset.

Since the ideal amplifier holds its output constant with respect to the dc bias problem, it is possible to see a Bode plot with a 10mVac input. I question why R1 is so low?

 

[garimella]

The article in the link provided gives UGW equation to be UGW= 1/2pi R1(C1+C2). I selected UGW = 5KHz ,which works out to be R1= 30 ohms. By the way how to solve the saturation problem. I tried tapping from the junction point of R2 and C1 and it seemed to be non saturating.

 

[crutschow]

I tried tapping from the junction point of R2 and C1 and it seemed to be non saturating.

What do you mean "tapping"?

 

[MikeMl]

The article in the link provided gives UGW equation to be UGW= 1/2pi R1(C1+C2). I selected UGW = 5KHz ,which works out to be R1= 30 ohms. ....

So make R2=500K and recompute

Does this have the same Bode Plot?

 

[MikeMl]

...By the way how to solve the saturation problem. I tried tapping from the junction point of R2 and C1 and it seemed to be non saturating.

There will be no saturation in "real" feedback system. The saturation you are seeing is because you are trying to simulate only the compensation circuit in isolation from the rest of the system.

 

[garimella]

Thanks for all your replies. But I was interested to see how this circuit behaves for DC. Type 2 should give zero error for both stationary and velocity input. Why does it saturate for DC(stationary)? By tapping I mean, measuring the voltage at the junction point of resistor and capacitor. What is the role of Vref?

 

[crutschow]

. Type 2 should give zero error for both stationary and velocity input.

That's only true when it's in a negative feedback loop, not when it's running open loop.

Why does it saturate for DC(stationary)?

Because any DC voltage will charge the integrator until the op amp saturates. It integrates the DC.
Do you understand how an integrator really works?

 

[garimella]

Yes I understand, but please give solution to prevent saturation for DC. What modifications are required in circuit.

 

[Wade Hassler]

A type 2 compensator is defined as having a pole at zero frequency. Changing that part would, to be insufferably pedantic, make it not a type 2 compensator.
It really does work closed-loop. You may want to watch for integrator wind-up(?) externally and reset when necessary.

 

[crutschow]

Yes I understand, but please give solution to prevent saturation for DC. What modifications are required in circuit.

No, you don't understand.
If you modify it, then it won't be a type 2 compensator.

An integrator will always saturate with a DC input (it integrates the DC value).
Why do you think it shouldn't?
Calculate the integral of a DC level and you will see.

 

[garimella]

Yes, Now I understand the role of integrator. One final question. In type 2 how does a zero manage to compensate for phase loss induced by a pole at origin. Because zero is placed somewhere else . For example, if TF = 1/s *(s+.01)/(s+.001) then we see that zero is at 10 rad. What happens to signal between dc to 10 rad? Will those signals make the circuit unstable

 

[garimella]

Yes, Now I understand the role of integrator. One final question. In type 2 how does a zero manage to compensate for phase loss induced by a pole at origin. Because zero is placed somewhere else . For example, if TF = 1/s *(s+.01)/(s+.001) then we see that zero is at 10 rad. What happens to signal between dc to 10 rad? Will those signals make the circuit unstable

 

[garimella]

Looking for a reply for Post #13