TTL and CMOS question.

[Eclipsed]

When power is removed from a TTL or a CMOS logic device, and the ground remains connected, do the outputs go to a logic 0 or do they go to a high impedance state? The reason why I ask is, I have a circuit with a microcontroller that uses a external rom.The address lines are multiplexed, when power is removed from the circuit, I want to be able to access the ROM through another microcontroller.Is it possible the unpowered multiplexer will hold some of the address lines(of the rom) at logic 0, causing a conflict with the added microcontroller?

 

[tavib]

:x
Yes, in case of CMOS a conflict will appear, and I think that is your case.
In case of TTL I am not sure, but is not recomended.
This is happen because every CMOS output transistor have a junction(diode) between D-S with cathode in D and anode in S, so because the Vdd=0V, when you will try to rise the output voltage from external, this diode become open and sink your current into Vdd wich is 0V.
The TTL outputs usually not have explicitly this diode but is posible to be added for protection reasons.

 

[Nigel Goodwin]

It's not a good idea, you need to make sure it's completely isolated, just removing the power isn't going to stop the chip affecting the rest of the circuit.

I would suggest you would need tri-state buffers to isolate the two parts, and disconnect it through those.

With some CMOS chips (PIC's are one) they have protection diodes on the inputs, one to ground, and one to +ve - the one to +ve will keep the chip powered from a high level input, so the chip may well still run when you remove it's power.