Troubleshooting a stopwatch on a FPGA in VHDL

Hi All,

I am a newbie. I am using Xilinx 10.1 to build a stopwatch for a class project. Everything compiled fine, but I am getting no output to my board! I have spent half the day troubleshooting and cannot seem to find the problem. I think it is in my controller file, but I am frazzled.

Can you look at the file and see if any bad logic jumps out at you? I had the controller written as process statements, but 10.1 doesn't synthesize that for some reason, so my TA wrote case statements instead (which I am a bit fuzzy on) There might be some weirdness due to the troubleshooting.

Thanks,

Sarah

I am a little quirky in that I will not open a zip file posted on a forum. So I ask you this. Have you created a test bench for you design. The difference between success and failure in FPGA design is simulate, simulate, simulate. The key to success in FPGA design is creating a good test bench.

Good luck

You can't get trojans/virii from zip files Mike, you can only get them from running .exe files. I'd be more worried about PDF's there have been several recent Adobe faults found if you don't have an updated version of the reader.