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Trouble Simulation Decoder in Verilog(Xilinx ISE)

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wuchy143

Member
Hi All,

I'm trying to simulate a simple decoder design I have written to go into a bigger project. It has 4 inputs and must generate a "0" output given a (0, 0, 0, 0) input. This is just one case I will have for it. I just want to see if I can get it to work for one case then put the rest in there and test them all. Any thoughts as to why my output is undefined "X"?

My .v code:
module decoder(SW, CLK_50M, COUNT_VAL);
input wire [3:0] SW;
input CLK_50M;
output COUNT_VAL;
reg COUNT_VAL;

always @(posedge CLK_50M)
begin
case(SW)
0000 : assign COUNT_VAL = 56818;
endcase
end

endmodule


Testbench Code:
`timescale 1ns / 1ps



module decoder_testbench_v;

//declaring inputs/outputs
reg clk;
reg [3:0] s;
reg out;


//generate free running clock 50MHz clock
always
begin
clk = 1'b1;
#10;
clk = 1'b0;
#10;
end

//instantiate my decoder
decoder my_decoder(.SW(s),.CLK_50M(clk),.COUNT_VAL(out));

initial
begin

#100

//test begins
s = 4'b0000;

end

endmodule
 
waveforms!
 

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