Transistor theory again ?

[tron87]

If you were designing a circuit to switch a low sided load using a npn transistor or n channel fet how would you calculate the following.

You know the load will draw 100ma at 12v so you choose a fet or trans which is well within the max current rating i get that bit but what about calculating the expected voltage on the emitter or drain when saturated in order to calculate the P how is that calculated ?

If a npn transistor is biased at a different voltage to that of the collector ie switching higher voltage with a low voltage then how is the expected voltage on the emitter calculated ?

 

[MikeMl]

If you were designing a circuit to switch a low sided load using a npn transistor or n channel fet how would you calculate the following...

I wouldn't. If I have a grounded load (Low-side), I would use a PNP or PFET.

 

[tron87]

What about for a high sided switch ?

 

[BrownOut]

You know the load will draw 100ma at 12v so you choose a fet or trans which is well within the max current rating i get that bit but what about calculating the expected voltage on the emitter or drain when saturated in order to calculate the P how is that calculated ?

Look at the transistor datasheet and get the VCESAT, that's the voltage that will be across the collecter and emitter when the transistor is saturated. It will be a curve over IC and temperature, but typically will be around 2.v-.3v for a bjt. Use that in your power caluclation. A FET will have a similar spec for VDS in "linear" or "triode" region.

If a npn transistor is biased at a different voltage to that of the collector ie switching higher voltage with a low voltage then how is the expected voltage on the emitter calculated ?

If the transistor is forward conducting, the emitter is always ~.7v below the base, for a NPN. Typically, when switching a high-side load, the emitter or source will be grounded and thus at 0V. If you need to limit the current, then use a resistor on the collector or drain side in series with the load.

 

[tron87]

For this mosfet where is it in this data sheet the expected VDS for when the mosfet is fully driven ?
http://www.datasheetcatalog.org/datasheets/90/283666_DS.pdf


What does the V(BR)DSS drain to sourch breakdown voltage mean ?

What does VDGR mean ?

 

[MikeMl]

Look at the red regions of the attached Fig6 and Fig8 from the IRF510 data sheet. If you operate it with Vgs ~10V, that shows what the Vds will be for whatever current (Id) your load draws. The power dissipation (heatsinking requirement) for the FET is the product of Vds and Id.

The IRF510 is an old, not very good NFET.

You never answered the comment about using a NFET if you have a Low-side, grounded load???? If you use an IRF510 in a circuit where the drain is connected to 12V, and you put the load between source and ground, the gate will have to be driven to +22V to saturate the FET.

Are you prepared to do that? It usually means using a charge-pump, or another power supply to get the higher gate voltage.

 

[BrownOut]

For this mosfet where is it in this data sheet the expected VDS for when the mosfet is fully driven ?

Look at figs. 6 & 8. Fig 6 is a typical chart of VDS v. ID for various values of VGS. For your application, you want the portion of the curve at the lower left hand on the chart. That's where you want your devide to operate. Fig 8 gives values for drain to source resistance. You can use this value, along with any load resistance to caluculate VDS(ON) using resistor voltage divider equations ie RDS = RDS/(RLOAD + RDS)

What does the V(BR)DSS drain to sourch breakdown voltage mean ?

That's the maximum operating voltage you may run the device at before it goes up in smoke.

 

[audioguru]

The curves on transistor datasheets are for "typical" devices and they are turned on for a very brief amount of time so they do not get warm. You cannot buy "typical" ones, you get whatever they have which might have low spec's but still pass the printed minimum or maximum spec's.

 

[tron87]

Back to basics for one second.
So the curls on a transistor data sheet are designed around the typical use of a transistor which is mainly turning stuff on and off very fast and amplification how do you recalculate the curls when you use one to turn something on for a 100% duty cycle ?


If i used pwm and adjusted the duty cyle on the gate of a fet would this reduce the drain current so 50 duty cycle 50% less current drawn in a time frame ?

 

[BrownOut]

Back to basics for one second.
So the curls on a transistor data sheet are designed around the typical use of a transistor which is mainly turning stuff on and off very fast and amplification how do you recalculate the curls when you use one to turn something on for a 100% duty cycle ?

That would be impossible. You can characterize your devices if you had the equiment, or prototype and test your circuit, or design in a margin of say 20% or use the worse case numbers from the specification chart or simulate your circuit while sweeping the parameters to determinehow the margins affect your design. There are a number of ways to get there. Usually giving your design a margin, especially when dealing with power calculations, is often the easiest. Remember, most of the times a circuit will be required to work over a range of ambeint temperatures.

If i used pwm and adjusted the duty cyle on the gate of a fet would this reduce the drain current so 50 duty cycle 50% less current drawn in a time frame ?

Yes, depending on the frequency of the signal and the time frame. You might actually need to go less than 50%, as you have turn nonzero on and turn off times, and the power dissipated will generally be more during these transient times.

 

[audioguru]

So the curls on a transistor data sheet are designed around the typical use of a transistor which is mainly turning stuff on and off very fast and amplification how do you recalculate the curls when you use one to turn something on for a 100% duty cycle?

No.
The curves show the characteristics for a "typical" transistor. Transistors with the same part number are not all the same.
Some have low current gain and others have high current gain or have "typical" current gain.
Minimum ones have a Vbe of 0.6V and maximum ones have 0.7V "typical" ones have 0.65V.
Some have a low saturation voltage loss and others have a high loss but "typical" ones are shown on a curve on a graph.
If i used pwm and adjusted the duty cyle on the gate of a fet would this reduce the drain current so 50 duty cycle 50% less current drawn in a time frame ?[/QUOTE]

If you design a circuit for "typical" transistors then the circuit probably won't work if the actual characteristics of the transistors are minimum or maximum.
But if you design the circuit for worst case but passing transistors then all the transistors will work in the circuit.