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Dear sir , the circuit in the attatched file can work normally?the ic1 is 7815, and the amplifier is LF353,
I don’t know the utility of the R1,R2 and C7, anybody help?
what's the path of the output current of 15V? THE current flow out, load then go where? to its GND then to the amplifier of out terminal? if the current go like this, the power IS limited by the LF353?
what's the path of the output current of 15V? THE current flow out, load then go where? to its GND then to the amplifier of out terminal? if the current go like this, the power IS limited by the LF353?
It LOOKS LIKE the opamps are meant to try to implement some ripple and noise (including load-induced variations) CANCELLATION scheme, by varying the regulator's ground reference out-of-phase with the load voltage variations. R1 and R2 are setting the opamp inverting amplifier gain. And C7 is just a DC-blocking capacitor for the amplifier input, so that only AC variations are fed to the cancellation amplifier.
NOTE that, assuming that the idea works, in a physical circuit implementation the opamps' pins 3 and 5 should have their own separate conductors that go all the way to the load ground point, separately from the conductor for the main filter capacitors' ground return (and also separately from each other). And the inputs for the C7 and C8 capacitors, similarly, should each have their own dedicated conductor that goes all the way to the load power supply pins. Otherwise, load supply and ground currents sharing the conductors with the "remote sense" signals will induce unwanted voltages, due to the parasitic inductance and resistance of the conductors, and will singnificantly degrade the regulation and cancellation. I would also probably want to have two separate conductors, one for each polarity's filter capacitors' ground return, that both go all the way to the load ground without connecting to anything else along the way.
I simulated your circuit, using the excellent, free LTspice (from linear.com).
I used an LT1086-12 fixed 12-volt regulator, since a model for that was readily available in LTspice. Note that I used a 100uF capacitor from the output of the regulator to ground (in parallel with 0.1 uF), instead of the 47 uF shown in your schematic. My AC (transformer secondary) input was modeled as an ideal sine source of 36V p-p, giving a regulator input voltage of a little over 17 volts, with about 166 mV p-p ripple. (Yeah, I should have used a lower input voltage.)
NOTE: The opamps' OTHER power supply pins, not shown in your schematic, need to be connected to the opposite power rail, so the opamps have dual-polarity supplies.
I simulated one channel only (i.e. +12V). I used a load resistor of 100 Ohms and placed a sinusoidal current source in parallel with it, drawing a sinusoidal current of 200 mA p-p, with a frequency of 1 kHz, to simulate a dynamic load.
Baseline test:
With the regulator's ground pin connected to ground (i.e. NOT like in your schematic), and the opamp's output disconnected from the regulator, the regulator's output voltage had a 1 kHz sine component of about 4 mV p-p, and a 120 Hz component of about 0.5 mV.
Cancellation test:
With the opamp connected as shown in your schematic (but with C5=47pF instead of 33pF), the regulator's output voltage was about 11.87v, with a 1 kHz component of only 120 uV p-p and a 120 Hz component of only 15 uV. (And increasing the value of the 33K resistor to 47K reduced the 1 kHz ripple to about 85 uV p-p, and reduced the 120 Hz ripple to about 11 uV p-p.)
So it looks like it works!
Lowering the values of R1 & R2 should make the opamp's DC output offset lower, making the regulators' outputs closer to the desired output voltage. Using low-leakage DC-blocking capacitors (C7 and C8) might also be a good idea.
Lowering the R1 & R2 (and R3 & R4) values also increases the speed of the startup of the supply. However, it degrades the low-frequency portion of the cancellation bandwidth. So C7 and C8 should probably be increased, proportionately, which negates the startup-speed increase. With the original component values, it took 3 to 4 seconds for the regulator output to reach its target value.
Note, also, that the 33pF feedback capacitor, which I would initially increase to 47 pF, in your schematic, should also be increased in proportion to any decrease in the value of the 33K feedback resistor R1 (or decreased if R1 is increased).
The last setup I tested had R1=10K, R2=300 Ohms, C5=150 pF, and C7=33uF. As noted, the opamp was powered with both supply polarities. (I used an LT1057A JFET-input opamp, since its model was already on hand, in LTspice.) With that setup, the regulator output voltage averaged about 11.96 volts, and had about 108 uV p-p of 1 kHz ripple, plus about 13 uV p-p of 120 Hz ripple.
There are lots of applications that need low output ripple+noise.
And a big capacitor would cost much more money than the opamp circuit, and take up more space, and not be as reliable. And I don't think it would perform as well.
I tried simulating the same supply, but with a 22000 uF capacitor added from the regulator output to ground, and with the opamp circuit completely disconnected, and with the regulator's reference pin connected to ground. With the same 0.2v p-p 1 kHz sine current source load in parallel with a 100 Ohm load resistor, the regulator's output voltage had about 1.6 mV p-p of 1 kHz and about 319 uV p-p of 120 Hz; i.e. MUCH worse than with the opamp cancellation circuit.
Even after changing the 2200uF smoothing cap to 3x 4700 uF, and changing the 22000uF output cap's ESR to .001 Ohms, there was still 1.4 mV p-p of 1 kHz and 59 uV p-p of 120 Hz in the output voltage. So it looks like the opamp cancellation circuit is at least much better at dealing with load-induced variations.
(Before anyone asks: In all of these simulations, I also modeled all of the capacitors' ESR, ESL, and leakage resistance parasitics. However, I did not model any wiring or pcb trace parasitic impedances, or any resistors' parasitic parallel capacitances.)
[Aside: Note that using a very large capacitor directly on the output of a three-pin regulator, as I mentioned simulating, above, is generally not very advisable, since it might negate some of the benefits of using the regulator, and might even cause high-frequency oscillation with some regulators, because of the larger cap's lower ESR (Equivalent Series Resistance). Using a 100 uF or so aluminum electrolytic seems to be a typical good maximum value (although much larger caps CAN be used, farther downstream, after the intervening wiring/trace impedance, with some possibly very good benefits). I noted that, in the last case, with 3x 4700 uF smoothing, when I removed the 22000 uF cap (w/unrealistically low .001 Ohm ESR, even) from the output, the 120 Hz component decreased from 59 uV to 48 uV p-p (although the 1 kHz load-induced component increased to about 4 mV p-p, from 1.4 mV p-p, as expected).]
wow,thanks gootee,I have learned a lot from your great work.
now ,I think that the simulation seems to be a useful tool for the circuit design.thank you very much .I want to add your reputation,but the system tell me like this 'You must spread some Reputation around before giving it to gootee again.' though I have add your reputation for your first post,but when I want to repeat the operation, failed. I don't know what's wrong.I'm sorry, gootee.
I will post more schematic for our learning .thanks everybody!
then, gootee, do you think the circuit will be helpful for reducing the ripple of the output when using the switcher instead of the linear regulator? (I never use the switcher, I don't know)
then, gootee, do you think the circuit will be helpful for reducing the ripple of the output when using the switcher instead of the linear regulator? (I never use the switcher, I don't know)
That type of "linear regulator with opamp ripple-cancellation" circuit topology should be able to help, if placed after an SMPS output. But I suppose it might need to be optimized for dealing with the fast spikes from some SMPS types. Maybe you can try simulating that, with LTspice, which also has a menu option (File-->Switch Selector Guide) that will automagically design an SMPS for you. And then you can modify the SMPS circuit and run more simulations, including the cancellation circuit. LTspice also includes many faster opamp models, e.g. LT1363/LT1364 with slew-rate of 1000v/us.
You could also download the OPA541 (E version) power chipamp's spice model, from Texas Instruments, at http://www.ti.com , and try using it as a dynamic load in your simulations. I usually do that, with the opa541 pushing large-amplitude square waves into a low-value resistive load, to "torture test" a power supply design.
And, if you add realistic wire or pcb trace impedances to the supply lines and ground returns, etc, you can see for yourself why a "star ground" topology is essential. (You can download my LTspice files that include star-ground-testing setups, at **broken link removed** , and copy and paste what you need, into your own LTspice schematics. That will make it easy to share and un-share ground-return-current paths, to experiment.) [By the way, always remember to include at least the parasitic series resistance, in capacitor and inductor models. In LTspice, you can just right-click on any L or C component, in the schematic, to set the parasitics' values.]
But, the first thing I would probably try, for a noisy SMPS output, is an LC or CLC lowpass filter. i.e. Place a high-current inductor (probably 10uH to 100uH) in series with the SMPS output and connect a large-ish electrolytic capacitor (maybe try 1000uF to 4700uF, as a start) to ground, after the inductor. You can also connect a similar capacitor to ground _before_ the inductor, to have a CLC lowpass topology (and that capacitor might already be there, in the SMPS). For my 60 kHz boost-mode SMPS, based on linear.com's LT1270A switcher chip, 2200uF/10uH/2200uF worked well-enough.
For the inductor, you could use, for example, one of the Bourns/J.W. Miller high-current toroidal models (2100, 2200, or 2300 series, e.g. Mouser.com # 2301-V-RC, 10 uH, 20 Amps, $2.78 qty 1). And, in my case, the 2200 uF 50V Nichicon UHE-series low-ESR caps worked well, with a 10uH inductor. e.g. Mouser.com # 647-UHE1H222MHD6, $1.81 qty 1.
Of course, if you are DESIGNING the SMPS, too, then you should also make sure that you have used snubber networks, if needed. In my simple boost-mode SMPS, I definitely needed a series RC snubber across the main diode after the switch, to get rid of some serious high-frequency ringing. Ltspice showed the ringing, very well, and was also used to help optimize the R and C values for the snubber (R and C can be calculated. But, usually, you can just pick an R value that won't waste too much power and then change the C value to get the best waveform.)
For "the best of both worlds", you can also add a linear regulator circuit, after the CLC filter. I have used an LD1084 (an LT1084 "knockoff") 5-Amp adjustable linear regulator, with a small electrolytic cap bypassing the adjust pin to ground and a 150 uF electro from output to ground (and also with all of the other components recommended in the datasheet), and, in simulations at least, got the switching noise + 120 Hz ripple down to about 15 uV p-p (Reality is always a little different. But it is very quiet.).
Sorry to have blathered-on, for so long, about all of that.
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