I was reading about the different types of flip flops and came to this section that I didn't quite understand and would appreciate clarification for:
The Edge Triggered D Type Flip-flop
Fortunately ripple though can be largely prevented by using the Edge Triggered D Type flip-flop illustrated in Fig 5.3.3.
The clock pulse applied to the flip-flop is reduced to a very narrow positive going clock pulse of only about 45ns duration, by using an AND gate and applying the clock pulse directly to input ‘a’ but delaying its arrival at input ‘b’ by passing it through 3 inverters. This inverts the pulse and also delays it by three propagation delays, (about 15ns per inverter gate for 74HC series gates). The AND gate therefore produces logic 1 at its output only for the 45ns when both ‘a’ and ‘b’ are at logic 1 after the rising edge of the clock pulse.
The way I think of it is that "a" and "b" will never be at logic 1. The moment the clock is high producing logic 1 at "a" there will be nothing at "b"; not for 45 nano seconds and then "b" will be inverted to logic "0" .
Unless I don't understand logic gates at all and what actually happens is that current flows through the gate producing logic "1" while the gate is doing its thing and finally inverts the logic to "0", but that just sounds wrong because that means that the gate will be producing the wrong logic if even for nano seconds.
Thanks
Kal
The Edge Triggered D Type Flip-flop
Fortunately ripple though can be largely prevented by using the Edge Triggered D Type flip-flop illustrated in Fig 5.3.3.
The clock pulse applied to the flip-flop is reduced to a very narrow positive going clock pulse of only about 45ns duration, by using an AND gate and applying the clock pulse directly to input ‘a’ but delaying its arrival at input ‘b’ by passing it through 3 inverters. This inverts the pulse and also delays it by three propagation delays, (about 15ns per inverter gate for 74HC series gates). The AND gate therefore produces logic 1 at its output only for the 45ns when both ‘a’ and ‘b’ are at logic 1 after the rising edge of the clock pulse.
The way I think of it is that "a" and "b" will never be at logic 1. The moment the clock is high producing logic 1 at "a" there will be nothing at "b"; not for 45 nano seconds and then "b" will be inverted to logic "0" .
Unless I don't understand logic gates at all and what actually happens is that current flows through the gate producing logic "1" while the gate is doing its thing and finally inverts the logic to "0", but that just sounds wrong because that means that the gate will be producing the wrong logic if even for nano seconds.
Thanks
Kal