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The Edge Triggered D Type Flip-flop

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kal.a

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I was reading about the different types of flip flops and came to this section that I didn't quite understand and would appreciate clarification for:

The Edge Triggered D Type Flip-flop
Fortunately ripple though can be largely prevented by using the Edge Triggered D Type flip-flop illustrated in Fig 5.3.3.

The clock pulse applied to the flip-flop is reduced to a very narrow positive going clock pulse of only about 45ns duration, by using an AND gate and applying the clock pulse directly to input ‘a’ but delaying its arrival at input ‘b’ by passing it through 3 inverters. This inverts the pulse and also delays it by three propagation delays, (about 15ns per inverter gate for 74HC series gates). The AND gate therefore produces logic 1 at its output only for the 45ns when both ‘a’ and ‘b’ are at logic 1 after the rising edge of the clock pulse.


The way I think of it is that "a" and "b" will never be at logic 1. The moment the clock is high producing logic 1 at "a" there will be nothing at "b"; not for 45 nano seconds and then "b" will be inverted to logic "0" .
Unless I don't understand logic gates at all and what actually happens is that current flows through the gate producing logic "1" while the gate is doing its thing and finally inverts the logic to "0", but that just sounds wrong because that means that the gate will be producing the wrong logic if even for nano seconds.


Thanks
Kal
 

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I can't really improve on the explanation given in your post. What you say is true for a PERFECT logic element. (ANY gate, inverter or buffer.) There is no such thing as a PERFECT logic element. (By PERFECT I mean that the output would change at the same instant in time as the input.) During the period of the propagation delay the output will not agree with the definition for the type of gate. (I.E. for an inverter the output will be the same logic level as the input during the propagation delay.)

Les.
 
Thanks Les I now realize where I went wrong. I started out with the assumption that the gate inputs had *no state* and couldn't understand how input "b" got from no state to a logic 1 when in reality the "b" was at its previous state of logic 1 when the clock was low.
 
That is correct; good to see you got there on your own. Logic chip outputs can have a "no state" condition, where both the pull-up and pull-down transistors are off. This is called a tri-state output, and is very common in memory chip arrays. But logic chip inputs do not like being unterminated or undriven. The want to see either a 1 or a 0, a high or a low, and if you don't give them a valid input they will make up one on their own, usually leading to a circuit error.

If you are familiar with analog circuit functions, your circuit is implementing a version of a differentiator. There is another variation that uses an XOR gate rather than an AND gate, but the result is the same.

ak
 
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