storage device for comparator output problem

[mikey17]

hello, i am an electrical engineering student at the university of guyana. i am working on a project, that involves the use of comparators. my problem is that i am unable to store the comparators output. i would like advice on a device that can be used to store the output of the comparator

 

[blueroomelectronics]

Store for how long?

 

[mikey17]

storage device for comparator problem (2)

Store for how long?

QUOTE=Laplace;1322424]Since the output of a comparator should be a digital logic level of 0 or 1, try a latch or a D-type flip-flop.[/QUOTE]

hey thank you for that advice it has solve part of my problem, with your advice i am now able to utilize a clocked latch to store the end result of every comparison by the comparator. i can use the latch as a sampler to samply the comparator output N times per second. the problem is that the latch is a one bit memory.

i need a device to ACCESS and STORE the output from the latch at a rate N times per second. if not the output from the latch will be lost after the next rising/falling edge of the clock.

i would prefer a device that can store the latch output for an indefinite period. this is so since i am interested in analysis the comparator output over a period of time. the comparator is actually a decision maker for a digital communication technique that i am doing some research on. in order to test the scheme i need to have the system run for a period of time, compare the information sent (which would be known ahead of time) with the comparator's output, (which is the received information). the longer the device can hold data for the better
do you have any idea of a device that can access and store the output of the latch for later use. your advice will be greatly appreciated.
thank you

 

[blueroomelectronics]

How fast is the data? Hz, kHz, MHz?

 

[mikey17]

i would prefer to operate in the MHz range since, the design is for a digital communication ides i am testing to see its effectiveness. the theoretical error probability calculations is about 1 in 1 000 000. i intend to build the system, test and document its performance.