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Stability of Linear LED current regulator?

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Flyback

Well-Known Member
Hello,

We wish to do stability testing on our linear LED current regulator. It is actually mains connected.

The designer tells us that he has some worry about instability occurring. He says that we should stick to a certain family of the Infineon range of FETs so that the circuit stays stable.
I must admit I have not had chance to do much stability testing with the hardware yet, but on the simulator, making even large changes to all the circuit values around this LED current regulator don’t appear to be bringing any instability at all.
Do you believe that the attached circuit diagram would be a valid test to check for instability of this current regulator?
The company will not mind me posting this bit of the circuit as its just a well known standard linear current regulator.

I also attach the LTspice simulation of the regulator.
 

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Tony Stewart

Well-Known Member
Most Helpful Member
looks ok to test thus way.

-all you really need is to measure load step and line transient response with overshoot energy. (watt-s) under all conditions and test or calculate Tj rise of LED. Because the phase margin changes during turn on and turn off. so Bode Plots are limited use.

instability depends on load capacitance in LED cable and diodes on off state.

Qg = 64 nC = CV, Ic=CdV/dt if we use Vgs =4=dV and dV/dt=0.4V/us so that CdV=Qg=64nC then dt=10us

thus Ig= 64n / 10us = 6.4 mA which is within IC drive limits.

so unless there are positive feedback parasitics, it should be fine

Proper probe methods with 5mm coaxial spring on 10:1 probe with clip gnd wire removed are essential.
 

Tony Stewart

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but the heat loss in the linear mode is a problem

if you add hysteresis then you have a PFM hysteric buck converter , rearranging LC
 

Tony Stewart

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I know L/R is .1/50 =0.02 s and Coss is small and damped by 1.2 ohms , so where do think the resonance comes from ? FET model Coss? 47pF+10k?


With Vf of 75* 3.2 = 240V (unless these are really cheap LEDs ;) @ 1V/1.2 A

the. MOSFET Vds *Id can be as high as (339 -240)/1.2= 82.5 watts !!

Put in a hysteretic choke and cap for 50kHz ,
- since ESR of LEDs is kN/Pd= k* 75/3W for k = 0.5 to 1 depending on ESR quality with N=75Series LEDs , then ESR= 13 to 25 Ohms for LED string, so choose Z(f) average on PFM series resonant choke to be around 25 Ohms Driver RdsOn modulates by duty cycle so Z_FET= RdsOn/ d.f. for d.f. near 75 to 90% (est.) thus low Q hysteric PFM buck regulator.

My latest hunch is that the Op Amp cannot drive Vgs fast enough with current limit so poor phase margin. I=20mA = CissdV/dt
 
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Tony Stewart

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Looks like my hunch was close and your client was correct. It's unstable. RdsOn is a bit too low ( I picked 900mOhm ) and drive current to gate is too low ( so I added complementary emitter follower to gate) with 2 pole compensation.

Then I can see some overshoot but resonant free.

I just realized, I dont really like LTspice for show N tell (PITA) but it does serve a purpose with device models.

Your solution ought to include;
  1. consider adding RC delay to 1V reference for startup overshoot reduction. e.g. 10k+10nF
  2. add LC filter to MOSFET drain to prevent LED capacitance resonance.
    1. from low Z switched MOSFET source creates high Q instability
    2. due to LED shunt capacitance before being turned ON and series LC parasitic resonance
    3. e.g. Drain to 1 uH series to 1 uF shunt to LED string cathode, finally eliminates all resonance.
 
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Tony Stewart

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If you had a RLC Impedance nomograph, I would make everything clear, where resonance comes from and how to see Q values instantly
 

Flyback

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51.69W yes, but it is not on all the time, only short duty, and in the real circuit there is less voltage headroom
 

ci139

Active Member
you use DC HV source and no capacitors - to smooth out the Sine at Zero + Nπ rad takes quite large capacity for 600mA
the GRID ward going line noise can be likely filtered out for switching supply or perhaps you may externally regulate @100Hz to pass/dismiss entire half cycles ?
anyway why did you turned to linear
 

ci139

Active Member
did some little test
ccr~msr_01.png ccr~msr_10.png
  • i don't see much noise caused back on line
  • though i donno what the regulations are in UK
  • nor do i design those things -- i know how to draw wave forms in spice painter (muhahaa haa ha haa ha ha ha)
  • near constant frequency the filter would be no head ace
  • the opamp's not a cheap one
  • the component stressing was not studied in this experiment !
 

Tony Stewart

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Most Helpful Member
did some little test
View attachment 106096 View attachment 106097
  • i don't see much noise caused back on line
  • though i donno what the regulations are in UK
  • nor do i design those things -- i know how to draw wave forms in spice painter (muhahaa haa ha haa ha ha ha)
  • near constant frequency the filter would be no head ace
  • the opamp's not a cheap one
  • the component stressing was not studied in this experiment !
To understand Conducted line noise, you must simulate I(V1(t)) not V1 which is incorrectly modelled with 0 Ohms..try again.
 

ci139

Active Member
simulate I(V1(t))
? any .asc that has such a setup -- a link to

hysteretic PFM switching
decoding ... Figure 1. Pulse-frequency modulation (PFM) control circuit.

e.g. Drain to 1 uH series to 1 uF shunt to LED string cathode, finally eliminates all resonance.
??? this also sets a startup overshoot to LED-s string - does not it
___________________________
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
... i was just thinking about opamp being fed from "different power source" ??
I mentioned with a precise amount of positive feedback. (hysteresis)
how to set up your op amp supply in conjuction with the Led-s supply .. the grounds and loops ... so you can do anything precise without going too deep to signal processing
simplified answer as "never confronted the issues with" - - will do fine
 
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Tony Stewart

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Most Helpful Member
? any .asc that has such a setup -- a link to


decoding ... Figure 1. Pulse-frequency modulation (PFM) control circuit.


??? this also sets a startup overshoot to LED-s string - does not it
___________________________
¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯¯
... i was just thinking about opamp being fed from "different power source" ??

how to set up your op amp supply in conjuction with the Led-s supply .. the grounds and loops ... so you can do anything precise without going too deep to signal processing
simplified answer as "never confronted the issues with" - - will do fine
Overshoot depends entirely on Q of RLC. If your want critically damped then Q=0.7 , if that is less efficient than you want, then choose Q=1 or slightly higher

Overshoot is allowed in LEDs for short durations no problem, so understand Imax and SOA, this is a "non-issue" in fast transients for LED's but maybe not so for all other devices.
 
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Tony Stewart

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it's the best low ESR cap , along with tantalum, but what about CM noise and efficiency.

Lack of specs to define "good" on overall design input/output is your problem. If you want linear define acceptable losses, if you want high eff. define circuit ripple current with series choke then low ESR cap.
 

Mosaic

Well-Known Member
Why is it req'd to have such a hi voltage NFET?
The LEDs drop a significant amount of voltage and in linear mode there is no switching transient.
 
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