csaba911 posted this schematic some time ago.
It addresses the RAM chip and WE using counters. The problem is, when counter is at zero (cleared), WE is enabled. then it gets disabled, and then it changes to address 1 and enables WE again at the same time.
Doesn't the address need to be stable before actually pulling WE down??
Does this circuit really work anyway??
thanks.
It addresses the RAM chip and WE using counters. The problem is, when counter is at zero (cleared), WE is enabled. then it gets disabled, and then it changes to address 1 and enables WE again at the same time.
Doesn't the address need to be stable before actually pulling WE down??
Does this circuit really work anyway??
thanks.