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Speaker Confusion

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PeterDove

New Member
Hi,

I have a SAM7 chip and am having some trouble understanding why my PWM behaves as it does with a speaker I am attempting to drive.

Its a 8 Ohm 0.2W speaker.

I was reading up that it was possible to rather crudely convert 8bit audio to PWM pulses and thus drive the speaker. I have attached the speaker directly to the PWM - no RC/Filter stuff going on-- I am just attempting to understand the principle.

From what I gather, modulating the Duty Cycle is supposed to change the frequency on the speaker. However all that seems to do is change the volume!

Only changing the frequency of the PWM seems to change the actually pitch of the speaker.

Am I doing something wrong?

Regards

Peter
 

Hero999

Banned
The PWM should be done at a much higher frequency than the audio bandwidth >40kHz.

The duty cycle should be varied in time with the signal you want to send to the speaker.
 

PeterDove

New Member
Confusion of terms

The PWM should be done at a much higher frequency than the audio bandwidth >40kHz.

The duty cycle should be varied in time with the signal you want to send to the speaker.
Thanks for the Information - can you help with the questions below? This all relates to the AT91SAM7S256 processor/

I am setting the PWM to a frequency of 40000hz by doing the following.

prescaler = (47923200(mck) / 8) / 40000 = 149

AT91C_BASE_PWMC->PWMC_MR = prescaler | (3<<8) // 3 is the code for MCK/8

So I have PWM at 40000hz

Question 1 : How does setting the period relate? The period seems to be a value of 0-65535.... does a period of 65535 mean the period lasts of 1 second? ie is it a case of a period of 1 = (40000 / 65535). I'm very confused about this.

Question 2 : How then does the duty cycle number relate to the period?

Hope someone can help... its all a bit unclear.

Regards

Peter Dove
 

Sceadwian

Banned
It's explained on page 446-447 of the PDF for your chip.
I don't follow it 100% but it looks like the actual frequency output of your PWM signal is going to be (MCK/8*period)\MCK
Duty cycle will be limited by the period value you have to set to get the frequency you desire, the higher the period you have to select to get the desired frequency the less bit depth you'll have in the duty cycle. There are calculations on those pages for that as well. Basically you'll want to use the lowest value clock prescaler you possibly can to allow the period value to be as high as possible, which will give you the most range in your duty cycle. If you can drive the PWM clock fast enough you may be able to get some decent quality audio. What frequency are you running your processor at?

Once you get the 'carrier' PWM frequency going you just set up a timer at say 44.1khz and feed the duty cycle register .wav data values. To test it simply use a timer to simple set the PWM duty cycle between high and low states at about 1khz.
 
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Sceadwian

Banned
One day I might get around to trying this out on an AVR with a PLL, it'll allow an 8 bit duty cycle at 100khz.
 

PeterDove

New Member
I guess I will have to run some experiments as I still dont follow the datasheet.

Brain hurts. I can follow the settings just now how it all hangs together.

The forumula you mention (MCK/8*period)\MCK - would produce a number like 0.0125 ish - is this the length in seconds of the period?

Peter
 

Sceadwian

Banned
It's pretty simple.
You have your pre-scaler, which you said you set to MCK/8

By default the PWM cycle starts off, at 0 the clock starts running and for every 8 MCK ticks the PWM timer will increment by 1, when it reaches duty cycle it will turn off, when it reaches period it will turn on and reset. There are bits to control the exact functioning of the PWM in the datasheet, there are different modes that being the simplest.

Say you have MCK of 20Mhz, thats 50ns per clock tick. You're using a prescaler of 8 so that's 400ns, 40khz has a time constant of 25usec \ 400ns = a period of 62.5 cycles. Can't do that obviously so round up to 63. That's only 7 bits for the PWM though not very good.

No prescaler, Ie running the PWM clock directly off of MCK gives you straight 50ns per 1 value of period so 25u \ 50 = 500 dead even for 40khz, which will give you a duty cycle range of 1-500 or just shy of 9 bits.

If you want 8 bits even so you don't have to do any data scaling from .wav files work the other way and you get a period of 256 * 50ns = 78125hz which seems reasonable to me. Not sure what it's gonna sound like, but make sure you put a low pass filter with a cutoff frequency of about 20khz in there and modulate the duty cycle with and audio tone you'll get something out.
 
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Sceadwian

Banned
It took me multiple tries and watching the PWM modules in a simulator before I actually realized what was going on. Keep in mind I didn't fully read the PWM module for your chip and I don't know much about the rest of the chip so that's just a basic idea of what's going on, your EXACT output may be different (inverted) than what I say simply because I don't know all the details. I also don't know how your chip is clocked IE how MCK relates to your actual crystal frequency.

This is one good reason to read the PDF for your chip from cover to cover at least once, you don't have to memorize everything but if you have a problem later down the road a light bulb might go off in your head about a note or something you read from one section that will help you out of a predicament. The thing about technical documents like that are you can really just glance through them read the note texts and kind of cross your eyes at the tables charts and math, the important stuff tends to stick.
 
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PeterDove

New Member
Hi,

So I actually managed to get it set up OK. But the same thing is still happening. I am getting a very high pitched sound, and changing the duty cycle simply changes the volume.

So I also need to change the Period?

Peter
 

Nigel Goodwin

Super Moderator
Most Helpful Member
I think you're missing the point?.

The PWM should run at a high (inaudible) frequency, initially with a 50/50 ratio.

You then need to update the PWM register that sets the mark/space ratio with your sound samples - if your sound sample is recorded at 10,000 samples per second, you need to copy them to the register at 10,000 samples per second, to keep the pitch of the sound the same. It's the rate that you write the samples to the register that determines the frequency of whatever is output - if you write at half the sample frequency the sound will be an octave lower, and take twice as long to playback.

Exactly what are you trying to write to the PWM, and how fast are you doing it?.
 

PeterDove

New Member
I did a very simple test...

I include the code and what I am expecting to hear


// Sets up the PWM so that its running at full clock speed
PWMC_ConfigureClocks(47923200, 0,MCK);
PWMC_ConfigureChannel(0, AT91C_PWMC_CPRE_MCKA, 0, 0);

// Period length is 4357 ticks - 47923200 / 4357 is about 11Khz
PWMC_SetPeriod(0, 4357);
PWMC_SetDutyCycle(0, 1);
PWMC_EnableChannel(0);
IdleCount2=0;

//So by gradually increasing the duty cycle I was expecting to hear notes changing.

while(1)
{
IdleCount2++;
if (IdleCount2>4357) IdleCount2=1;
PWMC_SetDutyCycle(0,IdleCount2);
for (j=20000;j!=0;j--); // a 100th of a second pause
}

I have begun some more experiements with faster PWM to take it beyond audible.
 
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Nigel Goodwin

Super Moderator
Most Helpful Member
Like I said, you haven't understood at all.

First off, the PWM must be MUCH higher, too high to hear.

Second, it's the rate of change of duty that creates the audible frequency, you're changing the rate at massively sub-audio frequencies - you're not going to get a speaker to work that low, and if it could it's well below anything you could ever hear.

Increase the PWM to 40KHz or 50KHz, and remove the time delay entirely, see what you hear then.
 

PeterDove

New Member
OK now I get it... it was the 'Rate of change of duty that creates the audible frequency' that set the lightbulb off.

Thanks - busy recoding now.

Peter
 

Sceadwian

Banned
And you still have to filter it, if you don't you'll get weird mirror rising and falling tones from all the harmonics involved in hard stepping a high frequency PWM signal.
 
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