SMPS Multi-output Phase

[dknguyen]

Hi all, I need to make a triple output buck converter. The clocks are going to be synced but I have the choice of aligning all switching edges with each other with 0 and 180 degree phase alignnments to eliminate beat frequency effects (clock jitter and high frequency PSRR problems as described here)

http://wwwd.national.com/national/PowerMB.nsf/(approved-attachments)/05F8ABEBFF14659F8825710F005C7DA1/$File/Beat+Frequency+Solution.pdf

Or I have the choice to phase align the clocks of the 3 outputs in 0, 120, and 240 degree phase alignments to reduce the RMS ripple on the input capacitor.

I'm not quite sure which one tends to be a better choice. Obviously phase aligning everything to be the same will eliminate beat frequencies but make input ripple worse. But that can be improved if you align the two lower current phases together and have the third higher current output 180 degrees phase shifted relative to that. So I'm not sure whether I should:

-0 degree phase for the two lower current outputs, and 180 degree phase for the higher current output
-0, 120, and 240 phase shift for everything

 

[indulis]

What's the output voltage and current?

 

[dknguyen]

1.2V, 3.3V, 5V at various current levels but by far the highest being 1.2V@2A, but this is being designed for 5A. Input voltage is 6V-24V.

However, after reading the article again, it seems to imply that the beat frequency and low PSRR against switching noise isn't a problem if the clocks are actually the same frequency (regardless of the particular phase alignment chosen). But after thinking about it, it seems that the beat frequency phenomenon and low PSRR for switching noise of other converters are two separate issues, but have to work together for switching noise to propogate to the converter's output.

Could anyone help my clear up my understanding of this? This is my understanding so far:
1. Different clocks will cause beat frequencies (ie. the switching edges of one converter will slowly move through the period of another converter through consecutive cycles)
2. Switching noise caused at the input by switching converters will appear at the output of other converters in parallel because PSRR is poor at high frequencies
3. If a switching converter is currently in the "off" phase then switching noise from other converter cannot be propogated to the output (is this right? it intuitively makes sense to me)

So I am drawing the following conclusions:
A. So if my understanding is correct, if the clocks were synchronized, then #1 would no longer be an issue making the switching noise more predictable since the swithing edge of one converter would always occur at the same time in the cycle of another converter.
B. If the phases were then aligned (in addition to clock syncing) so the switching edge of one converter occured during the on-time of another converter than the switching noise would be worse than scenario A due to #3 since it would always be propogated through with optimum efficiency without fail. However, though the magnitude of the switching noise is worse than A, it is more predictable since #1 does not cause the switching edge of one converter to slowly move through the period of another converter.
C. Similar to B, but now we align the phases so that all switching edges happen at the same time. All switching noise now occurs at the same so it is worse in a sense, but it is uncertain whether it is passed to the output since it is on the threshold of on-off for the converters.
D. So, theoretically, if you arranged the the switching edges of converters so they would only occur during the off-time of other converters, switching noise would never propogate. I say theoretically because this would require asynchronous switching or place limits on the the duty cycles.

 

[indulis]

You may want to consider somethng along the lines of:

https://www.electro-tech-online.com/custompdfs/2010/06/MAX15048-MAX15049.pdf

or

Linear Technology - LTC3859 - Low IQ, Triple Output, Buck/Buck/Boost Synchronous Controller

and make life simple

 

[mneary]

That LTC part looks really nice. I would investigate using Figure 15, modifying the turns ratio of L3 to change VOUT3 to 5V.

[edit]hmmm, maybe all you need to change is RB3?