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simulation on Ltspice of an half bridge inverter with a Igbt with diod in antiparallel

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it's not alternate. some advice?
The Schmitt trigger hysteresis appears to be causing an offset in the modulation duty-cycle.
Try increasing the sinewave to 90V and the pulse input to +/- 100V A1, to minimize the effects of the hysteresis.
Or use a comparator without hysteresis for A1.
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