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sigma delta

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bburra

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hi,

my thesis is designing a sigma delta A/D converter.
i am going to simulate and lay this converter.
the cmos technology i am using is 0.35u technology. so right now i have started designing the comparator for CMOS 0.35 u technology.
But our layout doesnt allow us to use negative source voltage. So, my prof has asked me to design the comparator which is biased at half the source voltage (3.3/2=1.65). so , my reference voltage for the comparator is 1.65 and the other comparator input when below 1.65 is treated as negative and above 1.65 and equal is treated as positive (as in the case when the reference voltage is zero volts and allows input to go above and below zero.) and given output accordingly.

i want my comparator to sense even small changes in the input voltage from that of the reference level and thus give a logic low or high output. So , will my choice of designing a sense amplifier biased at 1.65 volts be right?
or will the latched comparator work?

if i am not mistaken the hysterisis effect is small in the sense amplifier. in the latched comparator (diff amp+inverter), we should also include the hysterisis effect and design it.

do you have any suggestions about this?
if this is the case then i have to design all my blocks which are biased at 1.65v. am i right?

can you help me out in this issue?

Thanks.

---BHAVANI BURRA.
 
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