Shift Registers without latches

[lycosa]

I'm attempting to learn a bit about serial communication and I'm just running examples and ideas in a simulator. I was wondering...

If I am feeding 8 bits into a shift register, and I have a shift register that doesn't latch, what would someone recommend to latch the output as it shifts the last bit in..and before it begins to shift the bits out?

My guess.. is to use a counter to count out every 8 bits and send a signal to 2 set-reset latches (each chip having 4 latches available) as the first bit shifts into the 8th position.

Is there a better chip to accomplish this? (Other than the 74HC595. MultiSim doesn't have that chip in the database).

I do a bit of programming and my overall intention is to eventually feed a serial command that will latch outputs to transistors to turn on relays.. pretty common I would imagine. While I know I could learn PIC's (I've played with basic stamps), I want to learn the long way around so that when I start tackling PIC's, I'll have more of a foundation on exactly what is going on.

Also, after looking over the datasheet, I think UARTS are a bit out of my grasp still. I really just want to use a basic set of IC's to get the job done so that I can read the datasheets, look at the logic diagram, and realize exactly how the serial to parallel translation is taking place. I'm not attempting serial communication yet, just simulations.

If anyone has some ideas, I would appreciate it.

 

[ericgibbs]

hi,
Does Multisim have a either 273, 274, 373 or 374 these are all 8 bit latches

 

[lycosa]

hi,
Does Multisim have a either 273, 274, 373 or 374 these are all 8 bit latches

Thank you for the suggestion. Multisim does in fact have 273, 373, and 374.

After looking over the datasheets, it appears that the 273 and 374 aren't latched, but rather the output can be turned off until the first significant bit is in the last position on the shift register. Once that bit is in the last position, the output can be enabled on the 374 or the 'Master Reset' can be brought high on the 273, and then data can be read (but not latched at the output). I'm assuming that it's 'destructive' of the data in performance in that as the shift register 'shifts' the 8 bits out, the 273 and 374 will change their output states accordingly and latches will still be required if I wanted to control a set of relays.

The 373 does have a latched output and although it looks a little more complicated, I'm guessing that if the 'output enable' is kept high, the outputs are at a high impedance state. Once all 8 bits have been shifted into the shift register, the 'Output Enable' on the 373 can be brought low enabling output. At the same time, bringing the latch enable from high (transparent mode) to low will latch the input at the output. As long as the 'latch enable' and 'output enable' are kept low, the output pins are latched at their current state. Does this interpretation sound correct? If so, it'll be perfect for the application.

Thanks very much for your time.

 

[OlPhart]

Yup, doing this to drive a bank of relays Is common. So much so... look up an STP16CP05, but you'll learn more doing it "longhand".

 

[lycosa]

Thanks.. I've been messing around with the chips and I've pretty much got it down now in a simulation. I've got a long way to go still I suppose, but I'm learning so much more than I would by just hooking up a couple wires to a microcontroller. I've still got plenty of bugs to work out, but my circuits are getting there and things are starting to make much more sense. Not bad for a days worth of study.

 

[Dean Huster]

I have NEVER played with a simulator and know nothing about them. Do they include propagation delay in a digital device's operation? Asynchronous shift registers and counters absolutely depend upon a device's propagation delay for their operation.

 

[lycosa]

Yes, propagation delay is included in the software for carry aheads, etc.

The prop. delay isn't all that crucial (so far) in the basic circuits I'm constructing. The counter circuit that I'm using is just to count to 8, when the last bit is shifted into the shift register, so that I can time the latch part of the circuit. The counter then gets a reset until the next input is received at the shift register.

 

[ericgibbs]

Yes, propagation delay is included in the software for carry aheads, etc.

The prop. delay isn't all that crucial (so far) in the basic circuits I'm constructing. The counter circuit that I'm using is just to count to 8, when the last bit is shifted into the shift register, so that I can time the latch part of the circuit. The counter then gets a reset until the next input is received at the shift register.

hi,
You can use a 273 and 374 as 8 bit latches and are often used in that mode.

When you clock your shift register, say 8 shifts, generate a latch pulse to the 273/4 373/4 on the back edge of the 8th shift clock generate a latch enable pulse, this will hold the data steady, while you reload/shift a new 8 bits into the S/R.

 

[Mikebits]

Memory data buffers are often used in serial I/O, in essence they are latches.

 

[lycosa]

I don't know if I should start a new thread, but I've hit a roadblock that I can't seem to push through. I'm attaching a photo of the circuit that I'm building to this post so hopefully those that have been gracious enough to help out so far, might continue to help me through this.

**broken link removed**

Okay.. so here goes..

U1 is a shift register, U3 is an 8 bit latch.

I've got the circuit clocked and the bits are shifting in just fine.. and then shifting back out just as well.

What I've circled on the circuit is the 'latch enable' and 'enable output' pins. What I need to do with the circuit is to pull both those pins low when the First Significant Bit is in the 8th position (when the led lights up in the the 8th position). When that first bit is in the 8th position, I want to lock down that latch so the data will stay in the respective on/off positions until the circuit is reset. Resetting the circuit is easy, but I'm having a hard time figuring out what to use to get the circuit to latch once I have that first bit where I want it.

I've tried using a 4 bit synchronous counter with both asynchronous and synchronous reset, but when using a separate D Latch to try and hold the data, with an inverter to pull the signal low, I'm having timing issues and it's just plain...not working. I could really use some advice on what direction to go with this.

 

[ericgibbs]

hi lycosa.
The 74HC573 output enable should be connected directly to 0V, you are not using the the latch in a tri-state circuit.

Use a HEF4017 to count the clock pulses, its a Johnson counter and should be glitch free.
Clock the 4017 on the back edge of the clock pulse that is used for the 164, detect the 8th output of the 4017 and use that to enable/strobe the 573 latch and also Reset the 4017..OK.??

 

[lycosa]

Thanks, I'll give that a shot today when I get a chance. Last night I was getting close but I ended up with quite a few components to get what (seemingly) should have been not all that difficult. I still ended the night with the circuit not timing properly with the 8 count and when the latch.. well.. latched.

Thanks a lot for taking the time to help!

I'll post my results later.