4. I'm trying to simulate the circuit in a computer program before I build my actual circuit. So I will try to do everything that you teach me in simulator first. I think the program has got enough parts for me to simulate this circuit.
5. I intend to build this circuit for pc. (Data coming from PC). So I believe I need to use uC; however, I just need a concept to create the 16 bit SIPO circuit then I think it okay for me.
Thanks for the details, I got that diagram in micro cap. By the way, what is the latch and shift clocks? and also what is the purpose to use them? Can I fit in both with the same clock pulse? So in order to keep the circuit working, both GBAR and SRCLRBAR must be remained as logic "1" ? If I intend to make a 16 bits SIPO circuit, is that I need to fit QHS to the SER input in the next 74HC595?
Thanks for the details about that, any idea about the maximum bit that a single serial in parallel out shift register can handle? Is that possible to get a register to have a 64 or 128 or more bits shift in one single shift register? Thanks.