Continue to Site

Welcome to our site!

Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

  • Welcome to our site! Electro Tech is an online community (with over 170,000 members) who enjoy talking about and building electronic circuits, projects and gadgets. To participate you need to register. Registration is free. Click here to register now.

Sampling frequency for a DC signal?

Status
Not open for further replies.

picstudent

New Member
Precision current sensing help please?

I am using a 13 bit ADC to measure the voltage across a shunt resistor.
The 0 to .1V DC is amplified and offset to .7 to 3.2 volts approximately (centered around 2.048V reference).

Now planning to implement a anti-alias filter before ADC or multiplexer .(I have 12 channels to measure)

To filter out noise (low pass filter ) what should be the cut off frequency?
also how much is the relevance of sampling frequency in my case where I am measuring a DC potential?

My code usually reads ADC in a round robbin fashion.Should we stick to a particular frequecy for sampling in this type of applications?

Thanks
Roy thomas
 
Last edited:
If you're measuring DC, then you don't need to 'sample' - just one reading is all you would ever need. However, presumably it's a varying DC, such as the current feeding something, it's effectively AC and you need to sample often enough to prevent anti-aliasing, and filter the input accordingly.

I would still expect there's no need for any speed though?, so you're looking at a VERY low frequency filter, under 1Hz and sampling five times a second or so.

Are you sure you need 13 bits?, I would expect many of them to be lost in the noise.
 
The need from 13 bits comes out of the fact that I need .1mA resolution. Somehow I have to stick with that.I understood the complications.
My demand for more 'sampling' speed comes from another factor. My device is actually monitoring the current in shunt resistor like this in 12 channels. Each channel is is switched by a high side P channel MOSFET switch. My software has to manage the over current or short circuit protection also. So 12 channels to be read in a faster speed ,not for data logging but to switch off in case..
Is it practical? How much time we get to switch off a MOSFET in short circuit before damaging it?

Thanks
 
The need from 13 bits comes out of the fact that I need .1mA resolution. Somehow I have to stick with that.I understood the complications.

It's not just a question of 'complications', it's complications for no gain, you won't get 13 bit resolution or accuracy.

My demand for more 'sampling' speed comes from another factor. My device is actually monitoring the current in shunt resistor like this in 12 channels. Each channel is is switched by a high side P channel MOSFET switch. My software has to manage the over current or short circuit protection also. So 12 channels to be read in a faster speed ,not for data logging but to switch off in case..
Is it practical? How much time we get to switch off a MOSFET in short circuit before damaging it?

It sounds absolutely foolhardy doing (or trying to do) S/C protection in software - how long you have depends on the exact circumstances, but devices can fail incredibly quickly.

Bear in mind if you are reading (and displaying) at speed, then the lower digits are likely to just be a blur, making a further mockery of hoped for 0.1mA resolution.
 
It sounds absolutely foolhardy doing (or trying to do) S/C protection in software - how long you have depends on the exact circumstances, but devices can fail incredibly quickly.
Could you suggest a hardware S/C protection mechanism so that I can try to implement it. My problem is I have to implement that hardware 12 times. But I think no other way to solve the issue.

If the ADC did int work out (at least I will learn how to noise effects these systems. I cant even provide proper ground plane etc. I have only copper pour as ground in my double side PCB.) I think I will have to move on to 10 bit built in One in PIC
Thanks for the help
 
Simply use the voltage drop across the resistor to turn off the FET, using a comparator if necessary - so the same opamp to amplify the voltage drop, then a comparator.

But really you need to see the hardware and do measurements on it - you're just stumbling in the dark otherwise. Software S/C control may be perfectly fine?, it all depends on the circumstances, and what the FET's will withstand.
 
Simply use the voltage drop across the resistor to turn off the FET, using a comparator if necessary - so the same opamp to amplify the voltage drop, then a comparator.
Thanks. I think good for me,not much complications. I have a two stage opamp there to amplify and offset. I will tap for the comparator from the middle. by the comparator I can pull down the base of transistor which drives the opto which drives the MOSFET. Thanks again.
But really you need to see the hardware and do measurements on it

Please see the attachment if time permits.

Thank you
 

Attachments

  • OffState.jpg
    OffState.jpg
    115.7 KB · Views: 305
  • ONState.jpg
    ONState.jpg
    114 KB · Views: 236
Well an LM324 isn't a good choice (in fact it would be hard to find a poorer choice), it's a VERY old and noisey device.

Is there any absolute need for the sensing resistor to be 0.2 ohms?, a higher resistor would help to make noise less of a problem.
 
Well an LM324 isn't a good choice (in fact it would be hard to find a poorer choice), it's a VERY old and noisey device.

Which will be better? A reasonably prized (need not be cheap!) quad op-amp? ( I think I will stick with quad - 2 for amp and offset like I have drawn, 1 for comparator to S/C protection and one for Low pass filter! So one channel one package!)

Is there any absolute need for the sensing resistor to be 0.2 ohms?, a higher resistor would help to make noise less of a problem.

The load should get +60V. So my thinking was; high value, more drop.

Thanks
 
Which will be better? A reasonably prized (need not be cheap!) quad op-amp? ( I think I will stick with quad - 2 for amp and offset like I have drawn, 1 for comparator to S/C protection and one for Low pass filter! So one channel one package!)

You might try the Texas TL074/084 series, they are reasonably priced (even cheap) yet have good performance - you might be better having a separate first opamp, so you can pick one with a particularly low noise figure?.

The load should get +60V. So my thinking was; high value, more drop.

Again, does it ever actually require 60V?, and is the 60V supply already fixed?. 500mA through a 1 ohm will only drop 0.5V, less than 1% of the supply.

If I was building this (the original system or whatever) I wouldn't have specified the supply to be only just high enough, a day with low mains would drop the supply below specification.
 
Picstudent, have you wondered why the voltage on the gate of your MOSFET in the ON state is such an odd value? That voltage will vary according to the "gain" of the individual optocoupler. Depending on the specs (you didn't provide a part number), the MOSFET may not turn on, or it might break down the gate (Vgs = ±20V maximum).
 
Doing current limiting in software? LOL :D

Sorry but it's a silly idea.

If you want simple use a PTC resistor (poly-fuse/switch).

If you really want to stick with software the add fuse as a backup.
 
Picstudent, have you wondered why the voltage on the gate of your MOSFET in the ON state is such an odd value? That voltage will vary according to the "gain" of the individual optocoupler. Depending on the specs (you didn't provide a part number), the MOSFET may not turn on, or it might break down the gate (Vgs = ±20V maximum).

I have attached the data of opto I plan to use.
My understanding was to drive MOSFET with a gate voltage somewhere between 12 to 20Volts. So I set input current to 10mA for OPTO led and choose that dropping resistors to get a gate voltage below 20Volts.(In simulator I set CTR as 20 for opto - Proteus I am learning only, might have overlooked something, not sure!)
Should we need to 'saturate' the opto transistor? I think it needs more curent in led which is a waste (I felt!)
What is the best arrabgement here?

Thanks

Roy Thomas
 

Attachments

  • OptoQuad.pdf
    85.5 KB · Views: 203
Doing current limiting in software? LOL :D

Sorry but it's a silly idea.

If you want simple use a PTC resistor (poly-fuse/switch).

If you really want to stick with software the add fuse as a backup.

I do not have any obcession to software protection.I was of the idea that it was simple and practical. I change my mind now. Plans to use comparator based cut off (monitor the shunt rsistor voltage with a opamp comparator and pulls down the opto LED drive if current exceeeds.

Interested to know more about PTC.I think it is what they call 'resettable fuse', right?
 
I have attached the data of opto I plan to use.
My understanding was to drive MOSFET with a gate voltage somewhere between 12 to 20Volts. So I set input current to 10mA for OPTO led and choose that dropping resistors to get a gate voltage below 20Volts.(In simulator I set CTR as 20 for opto - Proteus I am learning only, might have overlooked something, not sure!)
Should we need to 'saturate' the opto transistor? I think it needs more curent in led which is a waste (I felt!)
What is the best arrabgement here?

Thanks

Roy Thomas
The CTR of the part in the datasheet can be between 50% and 600%. This means Vgs will vary between 23.5V and ≈55V. This exceeds the 20V maximum Vgs spec for your PMOS transistor.
Since you will get at least 5mA collector current in the opto, the simplest solution is to be certain the opto saturates at 5mA (or more), and Vgs is limited to 10V, which is adequate to turn on the PMOS. You can do this by making R12=2k and R13=10k. I am not implying that the PMOS will turn off fast enough to protect your power supply when using these values. That depends on the characteristics of your supply.
 
The CTR of the part in the datasheet can be between 50% and 600%. This means Vgs will vary between 23.5V and ≈55V. This exceeds the 20V maximum Vgs spec for your PMOS transistor.
Since you will get at least 5mA collector current in the opto, the simplest solution is to be certain the opto saturates at 5mA (or more), and Vgs is limited to 10V, which is adequate to turn on the PMOS. You can do this by making R12=2k and R13=10k. I am not implying that the PMOS will turn off fast enough to protect your power supply when using these values. That depends on the characteristics of your supply.

Thanks for the info. I changed like that.

Why this CTR is not have a typical value in data sheet? Only minimum and maximum there.
Is normally we use the minimum value?
May be in our case that is safe option right?

So that is ok . thanks

Regards
Roy
 
Here is my revised schematics

Thanks
 

Attachments

  • offmosfet.jpg
    offmosfet.jpg
    123.8 KB · Views: 212
  • OnMOSFET.jpg
    OnMOSFET.jpg
    125.5 KB · Views: 261
Status
Not open for further replies.

Latest threads

New Articles From Microcontroller Tips

Back
Top