Rise and fall time for a MOSFET

[dbk229]

Hello,

For school I have to drive a mosfet with a PWM signal to powered a little motor in 12V (MCC).

My problem is : what voltage I should apply on my mosfet and what parameter I have to take care of to have the better performance in speed.

I found a first document. I explains how to design high speed circuit :

https://www.electro-tech-online.com/custompdfs/2012/12/slup169.pdf

In the document I found this :

View attachment 69149

It explains the differents steps of the rise time.

I tried to find the equations to calculate the different time of the differents steps of the diagram.

During step 1 and 2 the capacitor Cgs is charging. I have a RC circuit with Rgate and Cgs so I should be able to calculte the time of step 1 and 2 (Am I right ?)

But I am stuck at step 3, I'm not sure how to calculate the time.

I found a second document. This one gave me the equation but with no explanation (see page 6):
https://www.electro-tech-online.com/custompdfs/2012/12/pwrt1208.pdf

So, if you have an idea or a document about how to find back the equation, thank you

 

[alec_t]

I think you are making this more complicated than necessary and don't really need to calculate those values for your project (unless you've been told to).
You are clearly aware that the FET gate exhibits capacitance Cgs. The time taken to charge that capacitance depends on Cgs and on the resistance R of the source of charging current. So to minimise the charge time you must minimise R and/or Cgs. That means selecting a FET with as low a 'Gate charge' or 'Input capacitance as is practical/cost-effective (check the FET's datasheet) and driving the gate from a low-impedance source (e.g. the output of an op-amp, or an emitter-follower transistor stage). Unless your chosen FET is a so-called 'logic-level' type a gate voltage of ~10V may be needed to switch it on fully.

 

[MrAl]

Hello,

For school I have to drive a mosfet with a PWM signal to powered a little motor in 12V (MCC).

My problem is : what voltage I should apply on my mosfet and what parameter I have to take care of to have the better performance in speed.

I found a first document. I explains how to design high speed circuit :

https://www.electro-tech-online.com/custompdfs/2012/12/slup169.pdf

In the document I found this :

View attachment 69149

It explains the differents steps of the rise time.

I tried to find the equations to calculate the different time of the differents steps of the diagram.

During step 1 and 2 the capacitor Cgs is charging. I have a RC circuit with Rgate and Cgs so I should be able to calculte the time of step 1 and 2 (Am I right ?)

But I am stuck at step 3, I'm not sure how to calculate the time.

I found a second document. This one gave me the equation but with no explanation (see page 6):
https://www.electro-tech-online.com/custompdfs/2012/12/pwrt1208.pdf

So, if you have an idea or a document about how to find back the equation, thank you

Hi,

You're stuck probably because that is the hardest part to 'calculate'. As alec mentioned, the practical significance of this calculation may be limited to theoretical studies rather than application but may be used to some degree anyway so i'll briefly note what this entails.

First, the model looks like a MOSFET with gate drain capacitance Cgd, gate source capacitance Cgs, drive resistance Rdr, and some inductance L in the drain circuit. The analysis takes slightly different forms based on the actual inductance. This somewhat simplified view allows us to examine the action of the device without paying too much attention to other details even though they might be important in a practical circuit.

During interval 3 what we have already though if you look at a schematic is an amplifier with feedback. What is happening is the drive voltage is trying to drive Cgs voltage higher and higher but Rdr and of course Cgs prevents that from happening immediately (exponential), but also we get another action as the gate voltage starts to rise because the transistor starts to turn on following the law of the transconductance of the device. This causes the drain-to-source voltage to fall and that causes feedback through Cgd and that causes current to flow in opposition to the driver current through Rdr and that is why we see the flat 'porch' portion of the gate source voltage. The falling drain source voltage appears across Cgd and as it changes fairly quickly the gate voltage looks somewhat constant so the entire dv/dt acts with Cgd to steal drive current, thus making the gate voltage appear flat for that period. This action effectively makes the gate-to-source capacitance look much larger and is also known as the "Miller Capacitance".

Because this is an amplifier with feedback we have to know a lot of things like the transconductance and the drain inductance so that we can calculate the actual wave shape, which taken as is, will be at least a second order ODE. So we're talking not simply an exponential, we're talking exponential and sine and cosine terms as solution. Of course this is entirely possible and doable for sure in the theoretical circuit, but how you apply that to the real world you'll have to look into yourself.

International Rectifier used to have an application note that goes into detail about this, it used to be AN-947, but i dont see it on their site. Perhaps they had an updated note that makes that one obsolete, but you can try looking and see what you find. That will tell you more than i can tell you here without going into a lot of equations. But be prepared to think outside the box a little where you wont be able to use just an exponential.

AH HA! ...
https://www.google.com/url?url=http...te+947&usg=AFQjCNHKQpLF2V9_ncocTp3AuPFpekiq4A

or do a search for "IR app note 947".

 

[dbk229]

Ok, thank you for the explanation, it's more clear now.
I found the app note, I'm going to read it