Question about recharge pulse in bootstrap high side mosfet driver

[Triode]

So I've been using a lot of these training documents from TI and others to learn design because really they seem more practical than most text books. I had a question about part of this document. I've been trying to get better at designing motor drivers. In this case for BLDC but it could apply to every half bridge based design.

https://training.ti.com/sites/default/files/docs/High%20Side%20Bias%20Challanges%20and%20Solutions%20in%20Half%20Bridge%20Gate%20Drivers.pdf

I'm confused about this part

for easier reference here is the circuit under consideration

Is this just reinforcing the point that you can't go 100% duty cycle, and that you must recharge the bootstrap periodically? Is there some way to calculate how frequently or how long this must be done, or do you usually just tune it experimentally by scoping the gate pin and watching for the voltage to drop too close to below saturation? I see the equations on page 8, and I can find the drain to source leakage current on the datasheet. But I'm not sure about gathering all of the quantities used in those equations other than experimentally.

Also, about that little dip at the top of the ramp for Voltage of Cboot. I get that it would drop rapidly while initially charging the mosfet gate. But why is it parabolic and recovers? There is no energy coming in anymore from the Cboot charge path that I notice, seems like it would drop sharply till the gate is charged then falloff slowly from quiescent current and gate source leakage, I don't see why it goes back up.

Thanks!

 

[SPDCHK]

Slightly off topic...

I built my own Buck converter 12VDC battery solar charger. In the beginning I used N-Channel MOSFETS (on high voltage side) because of the low RDS, BUT, this always required a bootstrap type circuit to get voltage over 22V for proper MOSFET operation. I have gone through many design changes, trying nearly every IC on the market to get the required voltages, (even using a 555), but I always had some sort of issue or problem.

I dumped all that and replace the N-Channel with P-Channel. I now have 80% less component needed to drive the P-Channel, (using logic level MOSFETS with Arduino), and the slightly higher RDS only affects the MOSFET on full duty cycle. I had a heat sink on the N-Channel before, so as far as design components concerned, adding the heat sink did not change the original BOM (Bill of Materials)

I have a few units installed, and operational for more than a year now.

 

[Diver300]

I have a few comments but I think that you probably need to test in real life.
I think that it is mainly pointing out that you can't go to 100% duty cycle.
The drain to source leakage will be practically zero. Some datasheets quote a maximum, but in real life it can be so small as to be hard to measure, and an unconnected gate on a mosfet may allow the MOSFET to stay on.
The driver circuitry may have a leakage that is quoted.
The graph is a simplification, not a measurement, so the form of the dip isn't going to be accurate. I think that the voltage will go down due to the current taken by the gate capacitance and any series resistance including the ESR of the bootstrap capacitor. The voltage will recover when the gate stops charging, before the long slow decline. The details of the waveform aren't important, but the dip is shown mainly so that anyone actually observing a real one with an oscilloscope isn't worried by seeing a dip there.
The rate of the slow decline may be increased a lot with the leakage of an oscilloscope probe or a damp connection somewhere.

 

[rjenkinsgb]

Also, about that little dip at the top of the ramp for Voltage of Cboot. I get that it would drop rapidly while initially charging the mosfet gate. But why is it parabolic and recovers?

When the upper FET first turns on, the load output from the half bridge or whatever circuit will still be low and there will be a finite delay as the voltage on that increases, before the bootstrap capacitor charge diode becomes reverse biassed.

If the FET gate turn-on completes fast enough, the cap may still be recharging after the energy transfer to the gate is completed.
That would explain the recovery after the dip.