Hi,
A continuation of my previous post where I learnt about driving N-FET's in high side, I since created a sync boost with a P channel and BJT driver circuit. This works well to ensure the gate always goes to full voltage and quickly.
However, in a higher voltage application the gate needs to be protected from visiting ground, or any point about 20V below full voltage. I can't figure out how to do it whilst retaining the switching speed that introducing resistors works against. Any ideas?
So;
if Vin = 40 and P-FET is off, gate should be > 20.
if Vin = 10 and P-FET is on, gate should be 10.
if Vin = 15 and P-FET is off, gate should be 0.
Andrew
A continuation of my previous post where I learnt about driving N-FET's in high side, I since created a sync boost with a P channel and BJT driver circuit. This works well to ensure the gate always goes to full voltage and quickly.
However, in a higher voltage application the gate needs to be protected from visiting ground, or any point about 20V below full voltage. I can't figure out how to do it whilst retaining the switching speed that introducing resistors works against. Any ideas?
So;
if Vin = 40 and P-FET is off, gate should be > 20.
if Vin = 10 and P-FET is on, gate should be 10.
if Vin = 15 and P-FET is off, gate should be 0.
Andrew
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