PWM P-channel Limit Gate Voltage "off" to Drain-5v

[ACharnley]

Hi,

A continuation of my previous post where I learnt about driving N-FET's in high side, I since created a sync boost with a P channel and BJT driver circuit. This works well to ensure the gate always goes to full voltage and quickly.

However, in a higher voltage application the gate needs to be protected from visiting ground, or any point about 20V below full voltage. I can't figure out how to do it whilst retaining the switching speed that introducing resistors works against. Any ideas?

So;

if Vin = 40 and P-FET is off, gate should be > 20.
if Vin = 10 and P-FET is on, gate should be 10.
if Vin = 15 and P-FET is off, gate should be 0.

Andrew

 

[alec_t]

Why do you have the Q2 base and emitter shorted in the sim?

 

[crutschow]

Below is your Spice circuit modified with a push-pull driver and a 12V Zener clamp to limit the maximum Vgs to -12V (blue trace).
Below V+ = 12V the zener has no effect.

Note that you have the P-MOSFET upside-down in your simulation.

 

[ACharnley]

Alec_t, I'd used two NFets to ensure the Fet gate always goes to 0. crutschow's is a better solution (and thank you for it).

 

[ACharnley]

For a bonus point, in the second picture is a step-up. How does one determine when the duty is of such that the inductor has saturated and is now shorting current through the fet?