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Pullups - Rule of thumb?

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UTMonkey

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Dear All,

I am currently working on a project which involves getting a microcontroller to talk to a DS1306 using SPI.

Nearly all datasheets (not just the DS1306) contain a typical wiring example, trouble is for IC's which require a pullup resistor there are no details (that I can determine) which help me select which value to use as a pullup.

Is there a rule of thumb to this? or can I derive a value based on how much the chip sources\sinks?

Thanks in advance

Mark
 
The value of the pullup resistor is determined by the input current of whatever logic family it drives.
The DS1306 has a TTL output low voltage (0.4V) with a maximum current of 4mA. So its pullup resistor could be 2k for feeding a TTL gate, 1.2k for feeding a 74LS TTL gate or almost anything more than 1.2k for feeding Cmos which is a microcontroller.
 
That's rather low for a CMOS pullup - one factor you need to consider is speed, the pullup has to charge the capacitance of the line it's pulling high, so for long traces you need smaller values.

For your application I would suggest 'somewhere' in the 10's of kilohms -18K, 22K, it's really VERY uncritical.

BTW, just got back from Chesterfield, my daughter was playing at Joplins. Be there again Monday, she's playing at The Winding Wheel.
 
audioguru said:
The value of the pullup resistor is determined by the input current of whatever logic family it drives.
The DS1306 has a TTL output low voltage (0.4V) with a maximum current of 4mA. So its pullup resistor could be 2k for feeding a TTL gate, 1.2k for feeding a 74LS TTL gate or almost anything more than 1.2k for feeding Cmos which is a microcontroller.
The TTL current is a current coming out of the TTL input which you have to sink to ground to provide a logic zero. (The TTL input is the emitter of an NPN transistor). Thus the pullup resistor is not feeding this current. The TTL input current for a logic high is only leakage current, which is typically in the tens of microamps.
 
An old TTL input needs up to 1.6mA to 0V to be a logic low.
A Cmos input needs no current but needs a voltage that is at least 0.3 times the supply voltage to be a logic low.
 
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